|DAT Call for Papers (CLOSED)
We appreciate your interest in submitting a paper to the 2025 VLSI TSA. Herewith forms and the necessary information are provided for your preparation of the paper submission.
• IMPORTANT DATES: (Note: All are based on Taiwan time, which is eight hours ahead of Greenwich Mean Time (GMT+8).)
1. Paper Submission Due Date: December 2 December 16, 2024
2. Acceptance Notifications: January 24, 2025
3. Author Registration: February 28, 2025
• Original and unpublished papers on all aspects are solicited, including but not limited to the following scope.
Ü SCOPE
♣ ANALOG, MIXED-SIGNAL, and RF DESIGN
• Analog and Mixed-Signal Circuits
• Data Converters
• Power Management Circuits
• Wireless Transmitter and Receiver Circuits
• Wired System and IO Design
• Sensor and Interface Circuits
♣ DIGITAL, MEMORY, and AI CHIP DESIGN
• Asynchronous and Neuromorphic Computing Circuits
• Communication Baseband Designs
• Computing-in-Memory
• Digital AI Chips
• Digital Circuits and ASICs
• Hardware Security and Trust Circuits for IoT and AI
• Low Voltage & Ultra Low-Power Circuits and Systems
• Memory Circuits and Systems
♣ APPLICATION, SOFTWARE and HARDWARE, and AI SYSTEM
• AI for Systems and Systems for AI
• CPU, DSP, and Multicore Architectures
• Domain-Specific Architectures and Accelerators
• Embedded System and Software
• Hardware-efficient AI Methods
• Multimedia Processing Designs
• SoC (System on Chip) and NoC (Network on Chip)
• Software/Hardware Co-Design and System Compiler
• SiP (System-in-Package) and Heterogeneous Integration
♣ DESIGN AUTOMATION and TEST METHODOLOGY
• AI for Design Automation & Test
• Behavioral, Logic, and Physical Synthesis
• Design Automation & Test for Analog/Mixed-Signal/RF, 2D/3D IC, Memory, Biochip,
AI Chips, and Emerging Systems
• Design for Manufacturability, Testability, and BIST
• Design Verification, Modeling, and Simulation
• Power/Thermal/Timing Optimization and On-Chip Monitoring
• Silicon Debug, Diagnosis, ECO, and Yield/Reliability Enhancement
• Test Generation, Compression, and Test Standards
♣ EMERGING TECHNOLOGY
• Circuit & IP Design Based on New Transistor Technology, e.g., Fork-Fin FET, Sheet FET,
GAA FET, and C-FET
• Cryogenic Circuits and Systems
• Flexible and Printable Electronics
• Medical/Bio-electronics/Bio-inspired Chip Designs
• Quantum Computing
• Silicon Photonics
Ü GENERAL INSTRUCTIONS
• Prospective authors must electronically submit the self-contained paper with figures
(23:59 GMT+8).
IEEE-style compatible, in PDF format only. Any submissions not adhering to the rules will
be rejected immediately without review.
• Before submitting your abstract/paper, please review the information on IEEE Intellectual Property
• The review process will be double-blind.
- Please do NOT reveal any authors' information (names, affiliations, email,
grant information, personal acknowledgment, etc.) anywhere in the initial manuscript.
You must also ensure that the metadata in the PDF does not include such information.
- All references, including authors' previous work, should be referred as 3rd-persons'
works. E.g., you should use "This paper presents a new method to improve
XXX's approach [1]." instead of "This paper presents a new method to improve our
previous approach [1]." Do NOT omit or anonymize references for blind review.
- The initial manuscript violating the double-blind review policy will be rejected.
• Accepted papers MUST be presented in person by one of the authors at the symposium,
and the presentation must be conducted in English. All accepted manuscripts in the
proceeding will be published in IEEE Xplore.
• Any changes on the title and author list or withdrawal after acceptance must be approved by DAT
Program Chairs.
• All paper presenters are required to register for the symposium.
• No-show papers will not be included in the symposium proceedings and will not be submitted to the
IEEE Xplore database.
• Please refer to the detailed information on the conference website for authors:
Ü STUDENT SUBSIDY
• Student Travel Financial support for attending 2025 VLSI TSA is available for full-time
student presenters living outside of Taiwan.
Ü BEST PAPER AWARD
• Three best papers will be selected this year through a rigorous evaluation process
conducted by the program committee and session chairs.