Best Paper Award
Starting 2009, an Award Committee is formed for the selection of the Best Paper Award each year. The selection criteria of the award include the technical contents and writing quality of the paper as well as the quality of the presentation at the symposium. The award will be presented to the selected paper in the following year's symposium.
2022 VLSI-DAT Best Paper Award Committee
Led by the Technical Program Committee co-chairs, Dr. Shigeki Tomishima, Dr. Racy Cheng and Prof. Chih-Tsun Huang, the award committee members consist of subcommittee co-chairs. The Award Committee will select the 2022 Best Paper Award based on the criteria including the technical contents and depth, quality of the paper as well as the quality of the presentation. The award will be announced after the conference and granted in the VLSI-TSA and VLSI-DAT Opening ceremony in 2023. The winner will be rewarded by a certificate and US$500 . Besides, it will also offer the registration fee waived of 2023 VLSI-DAT.
2021 Award Winners Congratulations !
The 2021 Best Paper Award will be granted in the VLSI-TSＡ and VLSI-DAT Opening ceremony in 2022 and the winner will be rewarded by a certificate and US$500 . Besides, it will also offer the registration fee waived of 2022 VLSI-DAT.
• An Adaptive Loop Gain Tracking Digital PLL Using Spectrum-Balancing Technique
Co-authors: Guan-Yu Su, Zhi-Heng Kang and Shen-Iuan Liu National Taiwan University • Chip Performance Prediction Using Machine Learning Techniques
Co-authors: Min-Yan Su1, Wei-Chen Lin1, Yen-Ting Kuo1, Chien-Mo Li1, Eric Jia-Wei Fang2 and
Sung S.-Y. Hsueh2
1 National Taiwan University 2 MediaTek Inc.
• Storage-Aware Scheduling Algorithm for Reservoir Switching Minimization on Digital Microfluidic Biochips
Co-authors: Ling-Yen Song, Chih-Shen Yeh, Chien-Nan Liu and Juinn-Dar Huang
National Yang Ming Chiao Tung University
2022 Best Paper Award Candidates
• D1-1 Single Chip of Electrostatic Discharge Detector for IC Manufacturing Field Control
Co-authors: I-Hsuan Wu and Ming-Dou Ker
National Yang Ming Chiao Tung University
• D1-2 An Adaptive Digital PLL Based on BBPFD Transition Probability
Co-authors: Zhi-Heng Kang, Yu-Chi Yen, Guan-Yu Su and Shen-Iuan Liu
National Taiwan University
• D2-1 Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy
Co-authors: Kang-Yi Fan, Jyun-Hua Chen, Chien-Nan Liu and Juinn-Dar Huang
National Yang Ming Chiao Tung University
• D2-2 Robust CNFET Circuit Sizing Optimization
Co-authors: Zahra Heshmatpour, Lihong Zhang and Howard M Heys
Memorial University of Newfoundland
• D2-3 Fast and Efficient ResNN and Genetic Optimization for PVT Aware Performance Enhancement in Digital Circuits
Co-authors: Kushagra Agarwal, Aryamaan Jain, Deepthi Amuru and Zia Abbas
IIITH, Hyderabad
• D5-1 A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement
Co-authors: Xingyu Wang, Ruilin Zhang, Yuxin Wang, Kunyang Liu, Xuanzhen Wang and Hirofumi Shinohara
Waseda University
• D6-1 Hardware-Friendly Progressive Pruning Framework for CNN Model Compression using Universal Pattern Sets
Co-authors: Wei-Cheng Chou, Cheng-Wei Huang and Juinn-Dar Huang
National Yang Ming Chiao Tung University
• D8-4 Distributed Sorting Architecture on Multiple FPGA
Co-authors: Yi-Da Hsin, Yen-Shi Kuo and Bo-Cheng Lai
National Yang Ming Chiao Tung University