TSA Best Student Paper Award

 
In 2005, the Symposium started the Best Student Paper Award annual contest. The selection will be based on the paper quality evaluated by technical committee members, as well as the presentation of the paper at the symposium. The paper should be presented by the key author who is a full-time student at the time of paper presentation. The Best Student Paper Award will be presented to the winning student at the next year’s symposium.
 
2024 TSA Best Student Paper Award Winners ~ Congratulations!
 
The 2024 TSA Best Student Paper Award will be presented at 2025 International VLSI Symposium on Technology, Systems and Applications opening ceremony and each winner will be rewarded by a certificate and US$500. Besides, the Symposium will also offer the winners the waiver of registration fee to attend the 2025 International VLSI Symposium on Technology, Systems and Applications.
 
• An RRAM-Based 40.6 TOPS/W Energy-Efficient AI Inference Accelerator with Quad Neuromorphic-Processor-Unit
for Highly Contrast Recognition
Co-authors:Y. L. Lin1, Y. R. Liu1, T. C. Kao1, M. Y. Lee2, J. C. Guo1, T. –H. Hou1,2 and Steve S. Chung1
National Yang Ming Chiao Tung University
Taiwan Semiconductor Research Institute
 
• A New Ultra-Low Voltage Metal Fuse for High Density OTP Applications
Co-authors:Li-Yu Wang1, Kuan-Ju Chen1, Perng-Fei Yuh2, Yih Wang2, Jonathan Chang2, Ya-Chin King1
and Chrong Jung Lin1
National Tsing Hua University
TSMC
 
Contact Optimization Through Annealing and Edge Functionalization Towards 2D TMD Nanosheet Devices
Co-authors: Meng-Zhan Li1,2, Terry Y. T. Hung2, Wei Sheng Yun2, Sui An Chou2, Chen-Feng Hsu2, T. Y. Lee2, Chao-Ching Cheng2,
Iuliana P. Radu2 and Minn-Tsong Lin1,3
1 National Taiwan University
2 TSMC
3 Academia Sinica
 
2025 TSA Best Student Paper Award Candidates 
 
• T2-1 OTP-Generated Physical Unclonable Function for Hardware Security of AIoT Devices in Logic CMOS Platform
Co-authors: M. Y . Lin , C. W. Liang, Y. K. Wang, P. H. Shih, J. C. Guo and Steve S. Chung
National Yang Ming Chiao Tung University
 
• T2-2 Logic-Compatible Low-Voltage Complementary Analog Memory by CMOS FinFET
Technology
Co-authors: Hsin-Hung Yeh, Min-Hsun Chuang, Jiaw-Ren Shih, Chrong-Jung Lin and Ya-Chin King
National Tsing Hua University
 
• T2-3 Experimental Characterization of Dopant Freeze-out Effect Enhanced Electrical Variability in Cryogenic 16-nm Complementary FinFETs
Co-authors: Jia Zhe Ao1, Rui Qi Lin2, Pin Jie Pu2, Chen Yan Lin2, E Ray Hsieh1,3, Chien-Nan Kuo3 and Pei-Wen Li3
1 National Tsing Hua University,
2 National Central University
3 National Yang Ming Chiao Tung University
 
• T4-1 CROSS-LAYER MODELING OF SELF-HEATING COUPLED RELIABILITY WITH BACK SIDE POWER DELIVERY NETWORK
Co-authors: Yu Li, Cong Shen, Sihao Chen, Runsheng Wang and Lining Zhang
Peking University
 
• T6-1 Superlattice HfZrO2 Ultra-Thin Poly-Si Channel (3.5 nm) Junctionless 1T FeTFTs Featuring Nearly Zero Memory Window Degradation Rate (2.8%) and Robust 10 K to 423 K Retention for 3-D NAND NVMs and Neuromorphic Systems
Co-authors: Dong-Ru Hsieh1, Zi-Yang Hong1, Huai-En Luo1, Li-Ting Chou1, Wei-Ju Yeh1, Jia-Chian Ni1Shang-Lin Hsieh1,
Ciao-Fen Chen1,2, Yen-Fu Lin2, Shun-Tsung Lo1 and Tien-Sheng Chao1
1 National Yang Ming Chiao Tung University
2 National Chung Hsing University
 
• T8-1 From MRAM to SP-MTJ: An Ultrathin Mo Insertion in Magnetic Tunnel Junction-based P-bits for Solving Combinatorial Optimization Problem
Co-authors: Yu-Hsuan Lin1, Ching Shih1,2, Ming-Chun Hong1,2, Chen-Yu Yang1,2, Guan-Long Chen2Hsin-Han Lee2, Yu-Chen Hsin2, Chiao-Yun Lo2, Sin-You Huang2, Ting-Syun Huang1, Cheng-Yi Shih2Shan-Yi Yang2, I-Jung Wang2, Yao-Jen Chang2, Shih-Ching Chiu2,
Yi-Hui Su2, Chih-Yao Wang2Kuan-Ming Chen2, Ho-Lin Tsai2, Jeng-Hua Wei2, Shyh-Shyuan Sheu2, Wei-Chung Lo2, Shih-Chieh Chang2 and Tuo-Hung Hou1
1 National Yang Ming Chiao Tung University
2 Industrial Technology Research Institute
 
• T8-2 Improved STT Efficiency with Ultrathin Magnesium Composite Free Layer for Energy-Efficient MRAM
Co-authors: Tsai-Yu Wu1, Chen-Yu Yang1,2, Yu-Ho Kao1, Ming-Chun Hong1,2, Guan-Long Chen2Hsin-Han Lee2, Yu-Chen Hsin2,
Chiao-Yun Lo2, Sin-You Huang2, Yu-Tong Zhan1, Cheng-Yi Shih2Shan-Yi Yang2, I-Jung Wang2, Yao-Jen Chang2, Shih-Ching Chiu2,
Yi-Hui Su2Chih-Yao Wang2Kuan-Ming Chen2, Jeng-Hua Wei2, Shyh-Shyuan Sheu2, Wei-Chung Lo2, Shih-Chieh Chang2 and 
Tuo-Hung Hou1
1 National Yang Ming Chiao Tung University
2 Industrial Technology Research Institute
 
• T10-1 Atomic Layer Epitaxial 2D Dielectric h-AlN as Interfacial Layer with Excellent
Leakage and EOT < 1 nm for TMD-FETs
Co-authors: Shin-Yuan Wang1, Yu-Chin Lin1, Yu-Che Huang1, Chenming Hu1,2 and Chao-Hsin Chien1
1 National Yang Ming Chiao Tung University
2 University of California