Tuesday, April 19, 1:40 PM~3:20 PM Ballroom D
D1 Advanced Analog Circuit Techniques

  • 1:40 PM~2:00 PM
    D1-1 Single Chip of Electrostatic Discharge Detector for IC Manufacturing Field Control
    I-Hsuan Wu and Ming-Dou Ker
    National Yang Ming Chiao Tung University
  • 2:00 PM~2:20 PM
    D1-2 An Adaptive Digital PLL Based on BBPFD Transition Probability
    Zhi-Heng Kang, Yu-Chi Yen, Guan-Yu Su and Shen-Iuan Liu
    National Taiwan University
  • 2:20 PM~2:40 PM
    D1-3 An Injection-Locked Clock Multiplier With Injection Strength Calibration
    Yen-Min Tseng, Yu-Chi Yen and Shen-Iuan Liu
    National Taiwan University
  • 2:40 PM~3:00 PM
    D1-4 A 5-GHz Sub-Sampling Phase-Locked Loop With Pulse-Width to Current Conversion
    Shao-Yu Shu, Chun-Hung Lin and Ching-Yuan Yang
    National Chung Hsing University
  • 3:00 PM~3:20 PM
    D1-5 An Asynchronous Zero-Crossing-Based Incremental Delta-Sigma Converter
    Yen-Pp Lai, Hao-Hsuan Chang and Tai-Cheng Lee
    National Taiwan University

Tuesday, April 19, 3:50 PM~5:30 PM Ballroom D
D2 Recent Advances on EDA

  • 3:50 PM~4:10 PM
    D2-1 Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy
    Kang-Yi Fan, Jyun-Hua Chen, Chien-Nan Liu and Juinn-Dar Huang
    National Yang Ming Chiao Tung University
  • 4:10 PM~4:30 PM
    D2-2 Robust CNFET Circuit Sizing Optimization
    Zahra Heshmatpour, Lihong Zhang and Howard M Heys
    Memorial University of Newfoundland
  • 4:30 PM~4:50 PM
    D2-3 Fast and efficient ResNN and Genetic optimization for PVT aware performance enhancement in digital circuits
    Kushagra Agarwal, Aryamaan Jain, Deepthi Amuru and Zia Abbas
    IIITH
  • 4:50 PM~5:10 PM
    D2-4 SlewFTA: Functional Timing Analysis Considering Slew Propagation
    Zong-Hua Tsai, Aaron C.-W. Liang and Charles H.-P. Wen
    National Yang Ming Chiao Tung University
  • 5:10 PM~5:30 PM
    D2-5 Circuit Routing Using Monte Carlo Tree Search and Deep Reinforcement Learning
    Youbiao He, Hebi Li, Jin Tian and Forrest Sheng Bao
    Iowa State University

Wednesday, April 20, 10:20 AM~11:20 AM Mezzanine A+B
D4 New Directions in Testing Technologies

  • 10:20 AM~10:40 AM
    D4-1 Improving IJTAG Test Efficiency and Security
    Sying-Jyan Wang3, Yen-Chang Shih3, Katherine Shu-Min Li2, Chen-Yeh Lin1 and Song-Kong Chong1
    Institute for Information Industry
    National Sun Yat-sen University
    National Chung Hsing University
  • 10:40 AM~11:00 AM
    D4-2 A Memory Built-In Peer-Repair Architecture for Mesh-Connected Processor Array
    Pai-Yu Tan2, Chih-Hsuan Tung2, Cheng-Wen Wu2, Mincent Lee1 and Gordon Liao1
    1Taiwan Semiconductor Manufacturing Company
    2National Tsing Hua University
  • 11:00 AM~11:20 AM
    D4-3 A Thermal Quorum Sensing Scheme for Enhancement of Integrated-Circuit Reliability and Lifetime
    Hong-Hao Wang, Po-Yao Chung and Cheng-Wen Wu
    National Tsing Hua University

Wednesday, April 20, 1:40 PM~3:00 PM Ballroom C
D5 Digital IPs for Emerging Applications

  • 1:40 PM~2:00 PM
    D5-1 A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement
    Xingyu Wang, Ruilin Zhang, Yuxin Wang, Kunyang Liu, Xuanzhen Wang and Hirofumi Shinohara
    Waseda University
  • 2:00 PM~2:20 PM
    D5-2 An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications
    Chi Liu, Shao-Tzu Li, Tong-Lin Pan, Cheng-En Ni, Yun Sung, Chia-Lin Hu, Kang-Yu Chang, Tuo-Hung Hou, Tian-Sheuan Chang and Shyh-Jye Jou
    National Yang Ming Chiao Tung University
  • 2:20 PM~2:40 PM
    D5-3 A Body Channel Communication Transceiver with a 16x Oversampling CDR and Convolutional Codes
    Ching-Che Chung and Yi-Ting Tsai
    National Chung Cheng University
  • 2:40 PM~3:00 PM
    D5-4 An FPGA-Based High-Frequency Trading System for 10 Gigabit Ethernet with a Latency of 433 ns
    Yi-Chieh Kao, Hung-An Chen and Hsi-Pin Ma
    National Tsing Hua University

Wednesday, April 20, 1:40 PM~3:00 PM Ballroom D
D6 Hardware-aware DCNN Modeling and Optimization

  • 1:40 PM~2:00 PM
    D6-1 Hardware-Friendly Progressive Pruning Framework for CNN Model Compression using Universal Pattern Sets
    Wei-Cheng Chou, Cheng-Wei Huang and Juinn-Dar Huang
    National Yang Ming Chiao Tung University
  • 2:00 PM~2:20 PM
    D6-2 Variational Channel Distribution Pruning and Mixed-Precision Quantization for Neural Network Model Compression
    Wan-Ting Chang, Chih-Hung Kuo and Li-Chun Fang
    National Cheng Kung University
  • 2:20 PM~2:40 PM
    D6-3 Efficient Segment-wise Pruning for DCNN Inference Accelerators
    Che-Chang Yang2, Yung-Tai Shih2, Chun-Chen Chen2, Chih-Tsun Huang2 ,Jing-Jia Liou2 ,Yao-Hua Chen1 and Juin-Ming Lu1
    1 Industrial Technology Research Institute
    2 National Tsing Hua University
  • 2:40 PM~3:00 PM
    D6-4 An Embedded CNN Design for Edge Devices Based on Logarithmic Computing
    Chong-Yin Lu2, Ren-Song Tsay2 and Weyshin Chang1
    Deep Mentor Technology
    National Tsing Hua University

Wednesday, April 20, 3:30 PM~4:50 PM Ballroom D
D8 Accelerators for AI Applications and Data Analytics

  • 3:30 PM~3:50 PM
    D8-1 Configurable Deep Learning Accelerator with Bitwise-accurate Training and Verification
    Shien-Chun Luo, Kuo-Chiang Chang, Po-Wei Chen and Zhao-Hong Chen
    Industrial Technology Research Institute
  • 3:50 PM~4:10 PM
    D8-2 28-mW Fully Embedded AI Techniques with On-site Learning for Low-Power Handy Tactile Sensing System
    Yuji Yano1, Hisashi Iwamoto1, Takuma Yoshimura1, Yoshihiro Nishida2, Tatsuya Mori3, Kiyotaka Komoku4, Hidekuni Takao2 and Kazutami Arimoto4
    1 Poco-apoco Networks
    2 Kagawa University
    3 FaMT
    4 Okayama Prefectural University
  • 4:10 PM~4:30 PM
    D8-3 Composite Fault Diagnosis of Rotating Machinery With Collaborative Learning
    Pavan Kumar MP, Cheng-Jyun Tang and Kun-Chih Chen
    National Sun Yat-sen University
  • 4:30 PM~4:50 PM
    D8-4 Distributed Sorting Architecture on Multiple FPGA
    Yi-Da Hsin, Yen-Shi Kuo and Bo-Cheng Lai
    National Yang Ming Chiao Tung University

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