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Tuesday, April 14, 12:50 PM~5:00 PM Ballroom D
J2 ： Interactive Paper Session
Chair(s)： Yu-Hsuan Lin, Macronix International Co., Ltd
Shanq-Jang Ruan, National Taiwan University of Science and Technology

  • 12:50 PM~5:00 PM
    J2-1 Enabling High-Speed, Low-Voltage Frequency and Phase Modulation with Complementary Field-Effect Transistors (CFETs)
    Sandeep Semwal and Pin Su, National Yang Ming Chiao Tung University
  • 12:50 PM~5:00 PM
    J2-2 Impact of Si-doped Concentration on the Positive Anode Stress Stability of β-Ga2O3Schottky Barrier Diodes
    Pei-Jung Wang, Thien Sao Ngo, Huu Phuoc Dang, Niall Tumilty, Ray-Hua Horng and Tian-Li Wu, National Yang Ming Chiao Tung University
  • 12:50 PM~5:00 PM
    J2-3 Synergistic Defect Characterization of Fe-FETs
    Paul U. Feiler1,2, Alexander Schmid1,2, Yannick Raffel3, Ricardo Olivo3, Shouzhuo Yang3,
    Maximilian Lederer3 and Johannes Heitmann1,2
    1 TU Bergakademie Freiberg
    2 Fraunhofer IISB
    3 Fraunhofer IPMS
  • 12:50 PM~5:00 PM
    J2-4 A Compact 3T1F FeRAM Compute Cell for In-Memory MAC Using Partial Polarization Switching
    Vikrant Singh1, Anand Bulusu2 and Girish Pahwa1
    1 National Yang Ming Chiao Tung University
    2 Indian Institute of Technology Roorkee
  • 12:50 PM~5:00 PM
    J2-5 Investigation of High-Breakdown p-GaN HEMTs and TCAD Verification of RESURF Technology
    Pei-Tien Chen1, Yu-Wen Lai1, Po-Tsung Tu1, Hao-Chung Kuo1, Lung-Hsing Hsu2, Chang-Hong Shen3, Po-Chun Yeh4 and Hsin-Chu Chen5
    1 National Yang Ming Chiao Tung University
    2 Taiwan Semiconductor Research Institute
    3 National Tsing Hua University
    4 Industrial Technology Research Institute
    5 National Sun Yat-sen University
  • 12:50 PM~5:00 PM
    J2-6 Transient Mechanism of Steep Slope Devices "GCCI SOI-Tr" and Proposal of Ultralow Leakage Structure
    Haruki Yonezaki, Takayuki Mori and Jiro Ida, Kanazawa Institute of Technology
  • 12:50 PM~5:00 PM
    J2-7 Enhanced HfO2-Based Ferroelectric FETs with NH3-Plasma Induced SiON Interfacial Layer
    Shouzhuo Yang1,2, Fred Schöne1, Cyun-Siang Lin1,3, Ankit Agarwal3, Raik Hoffmann1, Kati Kühnel1, Yannick Raffel1, David Lehninger1, Konrad Seidel1, Kuo-Hsing Kao3, Maximilian Lederer1 and
    Gerald Gerlach2
    1 Fraunhofer Institute for Photonic Microsystems (IPMS)
    2 Technische Universität Dresden
    3 National Cheng Kung University
  • 12:50 PM~5:00 PM
    J2-8 Cryogenic Characteristics of Isotopically Enrinched 28Si/SiGe Heterostructure Field-Effect Transistors
    Hsiang-Shun Kao1, Yu-Jui Wu1, Yu-Hsuan Huang1, Tsai-Tzu Lu1, Muskan Sangal1, Wei-Hsiang Kao1 and Jiun-Yun Li1,2
    1 National Taiwan University
    2 Taiwan Semiconductor Research Institute
  • 12:50 PM~5:00 PM
    J2-9 Effect of Ozone Annealing on the Characteristics of p-Type SnO TFT
    Kai-Sheng Lin1,2, Yu-Ying Lin1, Guan-Han Lin1, Hsiang-Chao Yang1, Tsung-Te Chou2,
    Chien-Wei Chen2, Chi-Chung Kei2, Fan-Yu Yen3, Wei-Yen Chen3, Feng-Ching Chu3,
    Feng-Cheng Yang3 and Chun-Hsiung Lin1
    1 National Yang Ming Chiao Tung University
    2 National Center of Instrumentation Research
    3 Taiwan Semiconductor Manufacturing Company
  • 12:50 PM~5:00 PM
    J2-10 Dual-Function Surface Topology: Optimizing Ohmic Contacts and Channel Mobility via Cycle-Controlled PEALD Ga2O3 on 20nm Si Nanosheet
    Bi-Xian Wu, Yi-Hsiang Chen, Heng-Jui Chang, Chi-Tai Hsieh and Tzu-Hsuan Chang,
    National Taiwan University
  • 12:50 PM~5:00 PM
    J2-11 Modeling and Optimization of the Channel-All-Around (CAA) FeFETs
    Pei-Ying Li, Hsin-Tzu Liao, Jia-Yang Lee and Min-Hung Lee, National Taiwan University
  • 12:50 PM~5:00 PM
    J2-12 Doping Engineering of p-GaN Gate HEMTs on Si
    Jun-Zhe Wang1, Kai-Chieh Chiu1, Sheng-Kai Chen1, Po-Chun Yeh2, Po-Tsung Tu2 and Jen-Inn Chyi1
    1 National Central University
    2 Industrial Technology Research Institute
  • 12:50 PM~5:00 PM
    J2-13 Comprehensive Inspection Techniques for Evaluating Mg Activation Anneal in p-GaN of GaN Power Devices
    Pao-Chi Yao1, Ru-Zheng Lin2, Hao-Jyun Tan2, Hua-Mao Chen1, Chih-Ming Lai1 and Yu-Jen Chen1
    1 Industrial Technology Research Institute
    2 Lunghwa University of Science and Technology
  • 12:50 PM~5:00 PM
    J2-14 Investigation of the High-Frequency Characteristics and Scaling Performance of AlScN/GaN and AlInGaN/GaN HEMTs
    Hao Lee1, Yuh-Renn Wu1, Po-Tsung Tu2 and Po-Chun Yeh2
    1 National Taiwan University
    2 Industrial Technology Research Institute
  • 12:50 PM~5:00 PM
    J2-15 Low-Frequency Noise Characterization in HfO2/Al2O3 Tunnel Junctions for Quantum and Detection Applications
    Bilel Chergui1, Abdelkader Aliane1, Hacile Kaya1, Fabien Laulagnet1, Messaoud Bedjaoui1,
    Melanie Dartois1, Christophe Porzier1, and Martin Kogelschatz2
    1 CEA-Leti
    2 CNRS-LTM, Université Grenoble Alpes
  • 12:50 PM~5:00 PM
    J2-16 Accurate and Scalable MOL CFET Parasitic R/C Extraction via EM-Based Deep Learning Framework
    Chia-Yen Lai, Kuan-Ju Chou and Yiming Li, National Yang Ming Chiao Tung University
  • 12:50 PM~5:00 PM
    J2-17 Strain-Driven Control of Carrier Injection at Pristine and Defective n- and p-Type Metal-TMD Interfaces
    Sheikh Mohd Ta-Seen Afrid, He Lin Zhao, Arend M. van der Zande and Shaloo Rakheja,
    University of Illinois
  • 12:50 PM~5:00 PM
    J2-18 Modeling and Characterization of Ferroelectric HZO Considering Imprint Mechanisms
    Hau Ting Tsai1, Guan Lin Liu2, Che Chi Cheng3, Min Hung Lee3 and Pin Su1
    1 National Yang Ming Chiao Tung University
    2 National Taiwan Normal University
    3 National Taiwan University
  • 12:50 PM~5:00 PM
    J2-19 Enabling Logic-in-Memory (LiM) Functionality with Junctionless FeFETs
    Neeraj Samant1, Arya Ameet Agavekar1, Dhruv Ganesh1, Rohit Kumar Nirala2, Manish Gupta1 and Abhinav Kranti2
    1 Birla Institute of Technology and Science Pilani
    2 Indian Institute of Technology Indore

  • 12:50 PM~5:00 PM
    J2-20 A Theoretical and Experimental Assessment of IMD2-H2 Correspondence Under Memory-Effects
    Arthur Vandroogenbroek1, Martin Rack1, Frédéric Allibert2 and Jean-Pierre Raskin1
    1 UCLouvain
    2 Soitec
  • 12:50 PM~5:00 PM
    J2-21 Multi-Head Cascaded Deep Neural Networks with Multi-Scale Loss for BSIM-CMG C-V and I-V Parameter Extraction in Advanced MOSFETs
    Sidhant V. Vazarkar, Abdullah M.H. Cachhi, Shreyan Ghosh and Girish Pahwa,
    National Yang Ming Chiao Tung University
  • 12:50 PM~5:00 PM
    J2-22 A Compact Model for Charge-Based Voltage Readout in Multi-Level Capacitive Memories
    Mochamad Januar, Zhao-Feng Lou and Min-Hung Lee, National Taiwan University
  • 12:50 PM~5:00 PM
    J2-23 Design of a Traveling-Wave Mach–Zehnder Modulator Based on a Periodic Cylindrical Dual-Layer Metal Electrode
    Yung Ju Huang, Hsiao Ting Chu and Yu Liang Liu, Macnica Galaxy Inc.
  • 12:50 PM~5:00 PM
    J2-24 Optical Non-Volatile Memory with TiAlXOY Trapping Stacks
    Wen-Ching Hsieh1, Toji Matsuda1, Dong-Ru Hsieh1, Chang-Jyh Hsieh1, Bing-Mau Chen1, Chih-Chao Yang2, Fuh-Cheng Jong3, Wei-Ting Tseng1, You-Chen Zhou1, Li-Hang Ho1, Xing-Yu Chen1
    1 Minghsin University of Science and Technology
    2 Taiwan Semiconductor Research Institute
    3 Southern Taiwan University of Science and Technology
  • 12:50 PM~5:00 PM
    J2-25 Oven-Controlled Bandgap: A Fully Integrated Temperature and Voltage Reference
    Matthias Eberlein, Fraunhofer EMFT
  • 12:50 PM~5:00 PM
    J2-26 Device-Circuit Co-Design of Variation-Resilient Read and Write Drivers for Antiferromagnetic Tunnel Junction (AFMTJ) Memories
    Yousuf Choudhary and Tosiron Adegbija, The University of Arizona
  • 12:50 PM~5:00 PM
    J2-27 Implementation of a Lightweight Compression Architecture for Real-Time UHD Video Integration on FPGA
    Bing-Yi Lin, Shanq-Jang Ruan and Yu-You Xie, National Taiwan University of Science and Technology
  • 12:50 PM~5:00 PM
    J2-28 Robust Token Merging for Vision Transformer
    Wan-Jung Chen1, Yun-Hao Yang1, Ya-Chi Peng1, Chao Wei Chang1, An-Yeu (Andy) Wu1,
    Shih-Hsu Huang2 and Mladen Berekovic3
    1 National Taiwan University
    2 Chung Yuan Christian University
    3 University of Lübeck
  • 12:50 PM~5:00 PM
    J2-29 Fixed-Point FPGA Accelerator for Reveal-Network Inference in Deep Image Steganography
    Nishith Akula, Sujit Ghantasala and Madhav Rao, International Institute of Information Technology (IIIT-Bangalore)
  • 12:50 PM~5:00 PM
    J2-30 Process Selection Strategy for Chiplet-Based 2.5D Systems under Design Constraints
    Zi-Wei Huang1, Yi-Ting Li1, Wuqian Tang1, Liang-Chia Cheng2, Yung-Chih Chen3 and
    Chun-Yao Wang1
    1 National Tsing Hua University
    2 Industrial Technology Research Institute
    3 National Taiwan University of Science and Technology
  • 12:50 PM~5:00 PM
    J2-31 From Specification to Layout: An AI-driven Automation Design Flow for Analog Circuits
    Fang-Yi Liu, Hsin-Yi Lee and Tai-Cheng Lee, National Taiwan University
  • 12:50 PM~5:00 PM
    J2-32 A Hybrid Optimization Framework for Automatic Design of Arbitrary-Topology Matching Networks
    Jing Leng, Wei Feng, Hongtao Xu and Ye Lu, Fudan University

Tuesday, April 14, 1:40 PM~3:20 PM Ballroom A
T1 ： Ferroelectric Memories
Chair(s)： Min-Hung Lee, National Taiwan University

  • 1:40 PM~2:00 PM
    T1-1 Lower Power HfZrO2 FeRAMs With In-Situ CF4 Plasma Treatment at TiN Bottom Electrode Featuring Superior Endurance and Robust Retention for Embedded NVMs
    Dong-Ru Hsieh, Yi-Hsiu Chen, Yi-Sin Rao, Li-Quan Yang, Chia-Chen Wan, Kuan-Lin Chen,
    Shang-Lin Hsieh, Li-Ting Chou, Yi-Chen Chiang, Nai-Fang Hsu, Chun-Jung Su and
    Tien-Sheng Chao, National Yang Ming Chiao Tung University
  • 2:00 PM~2:20 PM
    T1-2 WOₓ–HZO-PEALD-TiN Interface-Engineered Ferroelectric Capacitors with >2×10¹⁰ Endurance
    Agniva Paul1, Gautham Kumar1, Sunanda Thunder2, Apu Das1, Asim Senapati1, Hubert Lakner2 and Sourav De1
    1 National Tsing Hua University
    2 Technische Universität Dresden

  • 2:20 PM~2:40 PM
    T1-3 Reviving Etch-Induced Damage on Ge MFIS via NH3 Plasma: 138% 2Pr Boost, >1000× Faster Switching, and Robust Duty-Cycle Endurance
    Kuei-Yuan Chen, Po-Lun Lin, Chung-Jung Su and Pin Su, National Yang Ming Chiao Tung University
  • 2:40 PM~3:00 PM
    T1-4 Resistance Read Out of Sensing Configuration for HfZrO2 1T1R Ferroelectric Capacitive Memory
    Z.-F. Lou1, K.-Y. Hsiang2, Y.-T. Chang1, J.-F. Wang1, C. W. Liu1 and M. H. Lee1
    1 National Taiwan University
    2 National Yang Ming Chiao Tung University

  • 3:00 PM~3:20 PM
    T1-5 Achieving High Endurance in Cryogenic FeMFETs
    Cyun-Siang Lin1, Shouzhuo Yang1, Ankit Agrawal2, Jacob Syndikus1, David Lehninger1,
    Kuo-Hsing Kao2 and Maximilian Lederer1
    1 Fraunhofer IPMS
    2 National Cheng Kung University

Tuesday, April 14, 1:40 PM~3:20 PM Ballroom C
D1 ： AI Accelerators, CIM, and Intelligent Systems
Chair(s)： Shinichi Nishizawa, Hiroshima University
Tsung-Te Liu, National Taiwan University

  • 1:40 PM~2:00 PM
    D1-1 An 88.1TOPS/W Hidden-Neural-Network Processor for Anomalous Sound Detection
    Li-Yuan Chang, Ren-Hao Chiou, Heng-Siang Gao and Chia-Hsiang Yang, National Taiwan University
  • 2:00 PM~2:20 PM
    D1-2 A Cost-Efficient FPGA Implementation of Real-Time Target Detection and Robotic Arm Transport System
    Siyi Li, Weiwei Shi, Xiaocong Cao, Hongliang Chen and Haoren Qin, Shenzhen University
  • 2:20 PM~2:40 PM
    D1-3 A 38.21-TOPS/W SRAM-Based Digital CIM Macro for Bit-Level Sparsity-Aware MAC Operations
    Priyanshu Tyagi, Dhayan Dhananjaya Senanayake and Sparsh Mittal,
    Indian Institute of Technology Roorkee (IIT Roorkee)
  • 2:40 PM~3:00 PM
    D1-4 Design and Optimization of an Instruction-Level Reconfigurable FPGA-Based Low-Power DNN Accelerator
    Tao Zhuang1, Ke Ma1, Shinichi Nishizawa2 and Shinji Kimura1
    1 Waseda University
    2 Hiroshima University
  • 3:00 PM~3:20 PM
    D1-5 A 1781 GOPS Compute-In-Memory CIM Macro with a Novel Dual-Port 8T SRAM for Implementing Multiple Logical Operations
    Cheena Singhal1, Abhishek Goel1, Kartik shahi2, Palak Sharma2, Sparsh Mittal1 and
    Sudeb Dasgupta1
    1 Indian Institute of Technology Roorkee (IIT Roorkee)
    2 Graphic Era University

Tuesday, April 14, 1:40 PM~3:20 PM Mezzanine A+B
D2 ： Advances in EDA Methodologies
Chair(s)： Iris Hui-Ru Jiang, National Taiwan University
Harry H. Chen, MediaTek Inc.

  • 1:40 PM~2:00 PM
    D2-1 GNN-Augmented MaskPlace: Fast Convergence in Macro Placement through Metaheuristic-Synthesized Datasets
    Varad Bharadiya, Krutik Patel, Shannon Muthanna , Margasahayam Venkatesh Chirag and
    Madhav Rao, International Institute of Information Technology Bangalore (IIIT-Bangalore)
  • 2:00 PM~2:20 PM
    D2-2 Differentiable Sensitivity-Based Skew Scheduling Framework for Timing Optimization
    Hsin-Tzu Chang1, Wen-Hao Liu1, Yi-Chen Lu1, Anand Rajaram1, Iris Hui-Ru Jiang2 and Haoxing Ren1
    1 NVIDIA
    2 National Taiwan University
  • 2:20 PM~2:40 PM
    D2-3 HAWK: Machine Learning-Driven Waiver of Marginal Hold-Time Violations with Process-Variation Awareness
    Umang Singadiya, Pooja Beniwal and Sneh Saurabh,
    Indraprastha Institute of Information Technology Delhi (IIIT-Delhi)

  • 2:40 PM~3:00 PM
    D2-4 Cocktail Security Scheme for Patching the Bus Vulnerability of Chiplet ICs
    Jui-Hsien Wang1, Zheng-Hao Wang1, Shi-Yu Huang1 and Chi-Kang Chen2
    1 National Tsing Hua University
    2 Taiwan Electronic System Design Automation
  • 3:00 PM~3:20 PM
    D2-5 CFET-HMF: A Hybrid Metaheuristic Framework for Synthesizing Standard Cells of CFET
    Tengfei Zhang, Rundong Jia, Qianqian Huang and Ru Huang, Peking University

Tuesday, April 14, 3:40 PM~5:20 PM Ballroom C
D3 ： Efficient Accelerator Design for Training and Inference
Chair(s)： Yi-Chung Wu, National Yang Ming Chiao Tung University

  • 3:40 PM~4:00 PM
    D3-1 Training Approximate CNNs Using Block-wise Quadratic Surrogate Gradient
    Ke Ma1, Tao Zhuang1, Shinichi Nishizawa2, and Shinji Kimura1
    1 Waseda University
    2 Hiroshima University
  • 4:00 PM~4:20 PM
    D3-2 SoftApprox: A Hardware-Efficient SoftMax Approximation for FPGA-Based Transformer Inference
    Komaragiri Sai Vishwanath Rohit, Lohitaksh Maruvada and Madhav Rao,
    International Institute of Information Technology Bangalore (IIIT-Bangalore)
  • 4:20 PM~4:40 PM
    D3-3 '1'-bit Count-based Sorting Unit to Reduce Link Power in DNN Accelerators
    Ruichi Han, Yizhi Chen, Tong Lei, Jordi Altayo Gonzalez and Ahmed Hemani,
    KTH Royal Institute of Technology
  • 4:40 PM~5:00 PM
    D3-4 Truncation-Based Approximate Communication with Zero-Bypass for Efficient CNN Accelerators
    Tong-Yu Hsieh, Po-Kai Huang and Jun-Tsung Wu, National Sun Yat-sen University
  • 5:00 PM~5:20 PM
    D3-5 PixSA: Hardware Efficient Pixel-Level Systolic-Array Architecture Design for AI Workload
    Vibushita S, Mohit Jagini, Nanda Mitra Pammi and Madhav Rao,
    International Institute of Information Technology Bangalore (IIIT-Bangalore)

Tuesday, April 14, 3:40 PM~5:00 PM Mezzanine A+B
D4 ： Advances in Design Synthesis and Verification
Chair(s)： Jing-Jia Liou, National Tsing Hua University
Harry H. Chen, MediaTek Inc.

  • 3:40 PM~4:00 PM
    D4-1 A LLM-Assisted High-Level Synthesis Code Transformation from C++ to SystemC
    Ray-Che Hsu, Hung-Yu Kao, Chih-Tsun Huang and Jing-Jia Liou, National Tsing Hua University
  • 4:00 PM~4:20 PM
    D4-2 SHARP: A Comprehensive SystemC HLS Benchmark Suite and LLM-Assisted Testbench Optimization for RTL Coverage Closure
    Yi-Wen Tang, Shao-Tang Sung, Fang-Yu Hsu, Wen-Yu Teng, Hung-Yu Kao, Jing-Jia Liou and
    Chih-Tsun Huang, National Tsing Hua University
  • 4:20 PM~4:40 PM
    D4-3 FLAIR: A Framework for LLM-Driven Assertion Generation and Incremental Refinement
    Utkarsh Choudhary, Shivam Shukla and Sneh Saurabh,
    Indraprastha Institute of Information Technology Delhi (IIIT-Delhi)
  • 4:40 PM~5:00 PM
    D4-4 Exploring LLM-based Verilog Code Generation with Data-Efficient Fine-Tuning and Testbench Automation
    Mu-Chi Chen1, Po-Hsuan Huang2, Yu-Hung Kao2, Yen-Fu Liu2, Yu-Kai Hung2, Cheng Liang2,
    Shao-Chun Ho2, Chia-Heng Tu3 and Shih-Hao Hung2
    1 Academia Sinica
    2 National Taiwan University
    3 National Cheng Kung University

Wednesday, April 15, 10:20 AM~12:00 PM Ballroom A
T3 ： 2D Materials and Oxide Semiconductors
Chair(s)： Patrick Bressler, Fraunhofer Gesellschaft

  • 10:20 AM~10:40 AM
    T3-1 Suppression of Bias Instability in Monolayer WSe2 Top-Gate pFETs at Sub-1 nm EOT
    Yu-Wei Hsu1,2, Chen-Hsun Hsu1, Ching-Shuan Huang1, Nien-En Chiang2, Yu-Tung Lin2, Shao-Heng Chen2, Ting-Hua Wei1, Sin-Yue Li1, Ying-Zhang Chiu2, I-Chih Ni2, Chih-I Wu2 and Tsung-En Lee1
    1National Yang Ming Chiao Tung University
    2National Taiwan University

  • 10:40 AM~11:00 AM
    T3-2 Thermal Stability Enhancement in AlOx-passivated Ultrathin InOx FETs by Using PEALD-AlOx Dielectric
    Chia-Tsong Chen1, Kazuki Ishiyama1,2, Kasidit Toprasertpong3, Toshifumi Irisawa1, Wen Hsin Chang1, Ryutaro Nishino1, Shinji Migita1, Yukinori Morita1, Hiroyuki Ota1 and Tatsuro Maeda1
    1 National Institute of Advanced Industrial Science and Technology
    2 Nihon University
    3 The University of Tokyo

  • 11:00 AM~11:20 AM
    T3-3 Titanium as Oxygen Scavenging/Etching Stop Layers to Boost Ion of Self-Aligned IGZO Top-Gate Transistors
    Hsien-Ming Sung, Yu-Shan Wu, Yuan-Ming Liu, Ying-Jung Chen and C. W. Liu,
    National Taiwan University
  • 11:20 AM~11:40 AM
    T3-4 Contact-Length Scaling and Carrier Injection in ML MoS2 FETs with Hybrid Sb S/D Contacts
    Szu-Huan Hsu, Wen-Chia Wu, Chao-Hsin Chien and Yiming Li,
    National Yang Ming Chiao Tung university
  • 11:40 AM~12:00 PM
    T3-5 On Variability of ML/BL MoS2 FETs Induced by Channel-Layer-Thickness Fluctuation
    Kuan-Lin Lee and Yiming Li, National Yang Ming Chiao Tung University

Wednesday, April 15, 10:20 AM~12:00 PM Ballroom C
T5 ： Memory-centric Computing and Neural Networks
Chair(s)： Louis Hutin, CEA-Leti

  • 10:20 AM~10:40 AM
    T5-1 High-RA STT-MRAM for In-Memory Computing: From Device Engineering to Prototype-IMC Validation
    Ming-Chun Hong1, Hsin-Han Lee2, Guan-Long Chen2, Sin-You Huang2, Chiao-Yun Lo2, Yi-Hui Su2, Ho-Lin Tsai2, Shih-Ching Chiu2, Cheng-Yi Shih2, Yao-Jen Chang2, Chih-Yao Wang2, Shan-Yi Yang2, Yu-Chen Hsin2, Jeng-Hua Wei2, Shyh-Shyuan Sheu2, Wei-Chung Lo2, Shih-Chieh Chang2 and
    Tuo-Hung Hou1
    1 National Yang Ming Chiao Tung University
    2 Industrial Technology Research Institute
  • 10:40 AM~11:00 AM
    T5-2 A Novel Gate-injected Ferroelectric Tunnel FET with Ambipolarity Enabling 3D In-Storage Computing and Searching for LLMs
    Jin Luo, Shaodi Xu, Yuxin Lin, Qianqian Huang and Ru Huang, Peking University
  • 11:00 AM~11:20 AM
    T5-3 Novel Full Ferroelectric-based Continuous-Time Ising Machine with Ultra-Low Hardware Cost for Real-Time Combinatorial Optimization
    Weikai Xu, Qianqian Huang and Ru Huang, Peking University
  • 11:20 AM~11:40 AM
    T5-4 In-depth Energy Analysis of a Hybrid sMTJ/RRAM Ising Machine
    Hugo Levices1, Kamel-Eddine Harabi1, Louis Hutin1, Mathieu-Coumba Faye1, Damien Querlioz2, Mohammed Akib Iftakher2, Kevin Garello3 and Philippe Talatchian3
    1 Université Grenoble-Alpes, CEA-Leti
    2 Université Paris-Saclay, CNRS
    3 Université Grenoble-Alpes, CEA, CNRS

  • 11:40 AM~12:00 PM
    T5-5 Variability Prediction for Polycrystalline Devices based on Voronoi Diagram and Graph Neural Network Representation
    Yan Song1, Tao Du1, Wei Zhang2, Xuanyao Fong2, Guangxi Hu1 and Ye Lu1
    1 Fudan University
    2 National University of Singapore

Wednesday, April 15, 10:20 AM~12:00 PM Mezzanine A+B
D6 ： High-Speed Interface Circuits
Chair(s)： Po-Yu Kuo, National Yunlin University of Science and Technology
Hsin-Liang Chen, Tamkang University

  • 10:20 AM~10:40 AM
    D6-1 A 20 Gb/s 2VDD PAM-4 TX Output Driver With Core-Only Devices
    Che-Chia Tien and Tai-Cheng Lee, National Taiwan University
  • 10:40 AM~11:00 AM
    D6-2 A 64-Gb/s Baud-Rate PAM-4 Receiver With One-Tap DFE and Reference-less CDR
    Cheng-Fu Weng, Jhe-En Lin, Shih-Chang Ma and Shen-Iuan Liu, National Taiwan University
  • 11:00 AM~11:20 AM
    D6-3 A Near Zero-DC Readout Circuit for CMOS Image Sensors
    Tonny Do1, Robert Johansson2, Ruben Gomez-Merchan3 and Trung Thanh Nguyen2
    1 University of Oslo
    2 Sony Semiconductor Solutions
    3 University of Seville
  • 11:20 AM~11:40 AM
    D6-4 A 433MHz –33.2 dBm Sensitivity Fully Passive RF Wake-Up Receiver
    Yu-Chi Chiu, Ren-De Huang and Kuang-Wei Cheng, National Cheng Kung University
  • 11:40 AM~12:00 PM
    D6-5 A 14-bit, 125ps Temporal Resolution, CMOS Multi-Phase Dual Edge Digital Pulse Width Modulator
    Ying-Yu Yang, Yen-Yu Chen, Wei-Chih Wang, Yi-Ting Lin and Yu-Te Liao,
    National Yang Ming Chiao Tung University

Wednesday, April 15, 1:40 PM~3:20 PM Ballroom C
D7 ： RISC-V, Memory, and Secure Systems
Chair(s)： Yuan-Hao Huang, National Tsing Hua University
Kun-Chih Chen, National Yang Ming Chiao Tung University

  • 1:40 PM~2:00 PM
    D7-1 51.2 Gbps High-Entropy Random Number Generator Based on Hyperchaotic System
    Yu-Shuo Chang, Cheng-Bin Chen and Yuan-Hao Huang, National Tsing Hua University
  • 2:00 PM~2:20 PM
    D7-2 A 1KB oFEC-like Code Construction and Its Decoder Architecture for NAND Applications
    Yan-Teng Chuang, Erh-Yi Tu, Chi-Wei Huang, Chuan-Yun Lai, Yen-Chin Liao and Hsie-Chia Chang, National Yang Ming Chiao Tung University
  • 2:20 PM~2:40 PM
    D7-3 An Efficient Precoding Processor Based on RISC-V Architecture for MU-MIMO Systems
    Yu-Chi Lin1, Pei-Cheng Yeh1, Yi Ruei Li1, Wenn-Yi Lin2, Yi-Ling Tsai2, Shih-Hao Fang3,
    Chung-An Shen2 and Yuan-Hao Huang1
    1 National Tsing Hua University
    2 National Taiwan University of Science and Technology
    3 Industrial Technology Research Institute
  • 2:40 PM~3:00 PM
    D7-4 FPGA-Accelerated Risk Management for High-Frequency Trading with Two-Level Pipelined Architecture and Re-hash Tree Probing
    Katherine Shu-Min Li1, Chuan-Pu Chiou1, Cheng-Han Yu1, Sying-Jyan Wang2, Liang-Chia Cheng3, Chun-Lung Hsu4, Chien-Cheng Peng2, Bin-Ming Wang5 and Fang-Chi Wu1
    1 National Sun Yat-sen University
    2 National Chung Hsing University
    3 Industrial Technology Research Institute
    4 National Central University
    5 National Taipei University of Technology
  • 3:00 PM~3:20 PM
    D7-5 HLS Driven Obfuscation of DSP Hardware IP Designs Using Non-invertible Arbitrary Function and Reconfigurable Intertwined Obfuscation Logic
    Anirban Sengupta, Nabendu Bhui, Vishal Chourasia and Ayush Kumar Singh,
    Indian Institute of Technology Indore (IIT Indore)

Wednesday, April 15, 1:40 PM~3:20 PM Ballroom D
D8 ： Analog Techniques for Emerging Applications
Chair(s)： Ren-Shuo Liu, National Tsing Hua University

  • 1:40 PM~2:00 PM
    D8-1 A sub-1V, 82ppm/K Cryo-CMOS Voltage Reference Based on ΔVth in 22nm FDSOI
    Matthias Eberlein and Johannes Weber, Fraunhofer EMFT
  • 2:00 PM~2:20 PM
    D8-2 A Wide Temperature Range 12 µW 212-ppm/°K Bandgap Reference Circuit
    Kun-Jhe Li, Chi-Yin Chiu, Pei-Wei Li, and Chien-Nan Kuo, National Yang Ming Chiao Tung University
  • 2:20 PM~2:40 PM
    D8-3 A 0.01-mm² 10-bit 5-GS/s Current-Steering DAC Using Replica Current Generator for Cryogenic Applications
    Yi-Hsuan Chiu and Shen-Iuan Liu, National Taiwan University
  • 2:40 PM~3:00 PM
    D8-4 Precharge-Free Non-Volatile TCAM Using VCMA-MTJs with Op-Amp-Based Sensing and Embedded PUF Functionality
    Kevin Vicuña1,3, Marco Villegas2 and Lionel Trojman3
    1 University of Calabria
    2 Universidad San Francisco de Quito (USFQ)
    3 Institut Supérieur d’Électronique de Paris (ISEP)
  • 3:00 PM~3:20 PM
    D8-5 Non-Linear Tunable RO-based Time-to-Digital Converter for FeFET-based Computation-in-Memory Macro
    You-Chun Nian, Wei Lu and Po-Tsang Huang, National Yang Ming Chiao Tung University

Wednesday, April 15, 1:40 PM~3:00 PM Mezzanine A+B
T7 ： RF Device and Packaging Technologies
Chair(s)： Patrick Fay, University of Notre Dame

  • 1:40 PM~2:00 PM
    T7-1 Performance Enhancement of Nanosheet/Nanowire RF Transistor Arrays by Backside Metal Layout
    Chih-Hsuan Lu, Hsin-Cheng Lin, Tao Chou, Ching-Wang Yao and C. W. Liu,
    National Taiwan University
  • 2:00 PM~2:20 PM
    T7-2 Improved Pulsed OFF-state and SEMI-ON State Stability with Enhancement of Breakdown Voltage Using Sunken Floating Field Plate in RF GaN-on-Si MIS-HEMTs
    Meng-Che Tsai1, Huu Phuoc Dang1, Yi Yang1, Anant Johari1, Trinh Ngo Minh Thang1, Chi-An Chen1, Rajendra Singh2 and Tian-Li Wu1
    1 National Yang Ming Chiao Tung University
    2 Indian Institute of Technology Delhi

  • 2:20 PM~2:40 PM
    T7-3 Performance Boost in RF HEMTs Through a Polarization-Enhanced 10-nm InAlGaN Barrier with T-Gate Process Integration
    Lung-Hsing Hsu1, Ming-Hsuan Kao1, Wen-Hsien Huang1, Jia-Min Shieh1, Chih-Yao Chang2,
    Yen-Yang Hsieh2, Hao-Chung Kuo2, Chuan-Yeh Yu3, Yu-Lun Chueh3 and Chang-Hong Shen3
    1 Taiwan Semiconductor Research Institute
    2 National Yang Ming Chiao Tung University
    3 National Tsing Hua University
  • 2:40 PM~3:00 PM
    T7-4 > 60 GHz Antenna-in-Package with Integrated Lead-Frame Thermal Path and Low-Dk/Df Molding for Multi-Chip Systems
    Hao-Che Kao, Che-Sheng Yang, Po-Kai Chiu, Chih-Hao Lin, Meei-Yu Hs, Tao-Chih Chang and
    Yu-Min Lin, Industrial Technology Research Institute

Wednesday, April 15, 3:40 PM~5:20 PM Ballroom D
D10 ： From RISC-V Bring-up to Edge GenAI: Scalable Multiprocessors and FPGA Acceleration
Chair(s)： Ren-Shuo Liu, National Tsing Hua University

  • 3:40 PM~4:00 PM
    D10-1 Minimal Linux-Bootable RV64 Core: Microarchitecture Design and SoC Simulation
    Pei-Shan Hsiao, Yi-Teng Zhuang and Chung-Ho Chen, National Cheng Kung University
  • 4:00 PM~4:20 PM
    D10-2 A Scalable RISC-V Symmetric Multiprocessor
    Tzu-Chen Yang, Ye Chen, Lin-En Yen, You-Ting Li and Chun-Jen Tsai,
    National Yang Ming Chiao Tung University
  • 4:20 PM~4:40 PM
    D10-3 A High-Bandwidth Multi-Stream SIMD RISC-V Quad-Core Processor Based on an Asynchronous Ring Architecture
    Jih-Ching Chiu, Jiun-Wen Hsiao and Pin-Yao Chen, National Sun Yat-sen University
  • 4:40 PM~5:00 PM
    D10-4 Transformer Encoder Architecture for Edge FPGAs
    Mukesh Narayana Gadde, Kizheppatt Vipin and A. Amalin Prince,
    Birla Institute of Technology and Science, Pilani (BITS Pilani)
  • 5:00 PM~5:20 PM
    D10-5 Semantics-Driven Animation Generation Design for LLM Applications
    Yu-Lung Chen, Yi-Hsin Chen, I-Ting Chang, Chen-Hao Li and Chun-Lung Hsu,
    National Central University

Wednesday, April 15, 3:40 PM~5:00 PM Mezzanine A+B
T8 ： Power Devices and Thermal Materials
Chair(s)： Tian-Li Wu, National Yang Ming Chiao Tung University

  • 3:40 PM~4:00 PM
    T8-1 Monolithic Integration of SiC Gate Driver and VDMOS with P-Bottom Isolation and Recess Contact
    Chia-Lung Hung1, Chuan-Han Chen2, Yu-Chin Ting2, Ming-Han Wang2, Yi-Kai Hsiao1,
    Hao-Chung Kuo1 and Bing-Yue Tsui2
    1 Hon Hai Research Institute
    2 National Yang Ming Chiao Tung University
  • 4:00 PM~4:20 PM
    T8-2 Design on Power-Rail ESD Clamp Circuit to Reduce Standby Leakage Current in GaN-on-Si Process
    Chieh-Chen Ker, Chun-Yu Lin, Chao-Yang Ke and Ming-Dou Ker,
    National Yang Ming Chiao Tung University
  • 4:20 PM~4:40 PM
    T8-3 Exploring Interface State Density Variation in SiC MOSFETs Under Constant Voltage and Constant Current TDDB Stress Conditions
    Yu-Chieh Chen1, Wei-Cheng Lin1, Seokhuey Soo1, Yu-Jie Chiu1, Pin-Shiuan Kuo1, Surya Elangovan2, Chia-Lung Hung2, Yi-Kai Hsiao2, Hao-Chung Kuo2 and Tian-Li Wu1
    1 National Yang Ming Chiao Tung University
    2 Hon Hai Research Institute

  • 4:40 PM~5:00 PM
    T8-4 Vertical Aligned Hexagonal Boron Nitride with Ballistic Thermal Conductivity
    Ping Che Lee1, Diego Contreras Mora1, SeongUk Yun1, Dipayan Pal1, Amy Ross1, Mingeun Choi2, Mark Clark3, Larry Chen3, Haripin Chandra3, Ravindra Kanjolia3, Mansour Moinpour3, Satish Kumar2 and Andrew Kummel1
    1 University of California
    2 Georgia Institute of Technology
    3 EMD Electonics

Thursday, April 16, 10:20 AM~11:40 AM Ballroom A
T9 ： CMOS Processes and Devices
Chair(s)： Wei-Chen Tu, National Cheng Kung University

  • 10:20 AM~10:40 AM
    T9-1 Cryogenic Reliability Physics of 28nm HKMG nMOSFETs: Insights from A ΔDIBL Model and Gated-Diode Measurement
    Pin-Jie Pu1, Jia Zhe Ao2, An-Yao Hsu3, E Ray Hsieh3, Chien-Nan Kuo3, and Pei-Wen Li3
    1 National Central University
    2 National TsingHua University
    3 National Yang Ming Chiao Tung University

  • 10:40 AM~11:00 AM
    T9-2 Si Ultrathin Body Nanosheet by Sophisticated Wet Etching
    Wei-Jen Chen1, Ying-Qi Liu1, Tao Chou1, Chun-Yen Tseng1, Chih-En Fan2, Yi-Ming Mei1 and
    C. W. Liu1
    1 National Taiwan University
    2 National Tsing Hua University
  • 11:00 AM~11:20 AM
    T9-3 Stress Incorporation Using Single Diffusion Break for Next Generation Gate-All-Around Logic Technology
    Ashish Pal, Pratik B. Vyas, Subi Kengeri and El Mehdi Bazizi, Applied Materials, Inc.
  • 11:20 AM~11:40 AM
    T9-4 Strain Engineering for Next-Generation FDSOI MOSFET, Probing CESL Relaxation with Xe, Ar, and Ge Ion Implantation
    Louis David MOHGOUK ZOUKNAK, Blend MOHAMAD, Zdenek VHALUPA, Krunoslav ROMANJEK, Laurent LACHAL, Zdenek CHALUPA, Micael CHARBONNEAU, William VANDENDAELE, Vincent MANDRILLON, Frederic MAZEN, Arnaud ANOTTA, Nicolas GAUTHIER, Denis MARIOLLE, Laurent BREVARD, Laurent BRUNET, Philippe RODRIGUEZ, Blandine DURIEZ and Marie-Claire CYRILLE, Université Grenoble Alpes / CEA-Leti

Thursday, April 16, 10:20 AM~12:00 PM Mezzanine A+B
T12 ： Emerging Memories and New Applications
Chair(s)： Kazuhiko Endo, Tohoku University

  • 10:20 AM~10:40 AM
    T12-1 A High-Endurance 28nm HKMG Bipolar 2T eRRAM Fabricated Without Extra Masks: Insight into Filament Evolution via RTN Measurement
    Yi Xiang Huang1, Yu Hsien Lin1, Po Hsiung Huang1, Chi Da Lu1, and E Ray Hsieh2
    1 National Central University
    2 National Yang Ming Chiao Tung University

  • 10:40 AM~11:00 AM
    T12-2 Metal-Insulator-Metal Capacitors with Low Leakage Current and Low CET for DRAM Applications
    Jhih-Yuan Liang, Yu-Rui Chen and C. W. Liu, National Taiwan University
  • 11:00 AM~11:20 AM
    T12-3 Smart Pixel with TCReRAM: Tunable Capacitance for Analog Conversion Gain in Next-Generation Imaging Systems
    Shubham Pande1, Salil Chourasia1, Krisha Suthar1, Sandeep Kumar1, Veeresh Deshpande1,
    Andrea Padovani2, Luca Larcher3, Gaurav Thareja3 and Bhaswar Chakrabarti1
    1 Indian Institute of Technology Madras (IIT Madras)
    2 University of Modena and Reggio Emilia
    3 Applied Materials
  • 11:20 AM~11:40 AM
    T12-4 ZnO/Al2O3 Heterojunction Based Optoelectronic Neuro-inspired Memristor
    Saransh Shrivastava, Yu-Hang Poh, Chen-Wei Chang, Ke-Yue Wen, Stephen Ekaputra Limantoro and Tseung-Yuen Tseng, National Yang Ming Chiao Tung University
  • 11:40 AM~12:00 PM
    T12-5 Low-Temperature Hybrid Bonding Optimization for Ultra-Wide I/O AI DRAM Stacking
    Wei-Yang Huang, Yung-Yu Kuo, Yi-Jen Lo, Chia-Chun Liao, Jui-Feng Chang and Chiang-Lin Shih, Nanya Technology Corp.

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