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Tuesday, April 14, 3:40 PM~5:10 PM Ballroom A
T2 ： Wide Bandgap Devices
Chair(s)： Ionut Radu, SOITEC

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    3:40 PM~4:10 PM
    T2-1 Enabling Distributed Intelligence Beyond Conventional Scaling: New Materials, Devices, and Autonomous Microsystems
    Tomás Palacios, Massachusetts Institute of Technology (MIT)
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    4:10 PM~4:40 PM
    T2-2 8-Inch Open Innovation SiC Pilot Line and Technology Platform for Power Electronics in A*STAR, Singapore
    Gong Xiao, A*STAR and National University of Singapore
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    4:40 PM~5:10 PM
    T2-3 Rotational Domains in Heteroepitaxial β-Ga2O3 Films Grown by MOCVD
    Filip Gucmann, Slovak Academy of Sciences

Wednesday, April 15, 10:20 AM~11:50 AM Ballroom B
T4 ： Ferroelectric Devices and Applications
Chair(s)： Kai Ni, University of Notre Dame

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    10:20 AM~10:50 AM
    T4-1 Negative Capacitance Engineering for High-Reliability QLC Charge-Trap Flash: Interlayer and Band-Engineered CTL Approaches
    Sanghun Jeon, Korea Advanced Institute of Science and Technology (KAIST)
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    10:50 AM~11:20 AM
    T4-2 Ferroelectric Memories for Storage and Computing
    Thomas Kämpfe, TU Braunschweig and Fraunhofer IPMS
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    11:20 AM~11:50 AM
    T4-3 Embedded Hafnia-based Ferroelectric Devices and Applications
    Sou-Chi Chang, Intel Foundry

Wednesday, April 15, 10:20 AM~11:50 AM Ballroom D
D5 ： AI Processor Design
Chair(s)： Ren-Shuo Liu, National Tsing Hua University

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    10:20 AM~10:35 AM
    D5-1 High-Efficiency Arithmetic FPU and Compute-in-Memory Solutions for AI and HPC MCUs
    Jui-Jen Wu, Arete Microelectronics Inc.
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    10:35 AM~10:50 AM
    D5-1 High-Efficiency Arithmetic FPU and Compute-in-Memory Solutions for AI and HPC MCUs
    Shan Chi, Centreon Corporation
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    10:50 AM~11:20 AM
    D5-2 Enabling affordable Chip Design with Open Chiplet Atlas™ Ecosystem
    Zhimin Chen, Tenstorrent Inc.
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    11:20 AM~11:50 AM
    D5-3 Expedite Design Space Exploration (DSE) with Abstracted Performance Modeling
    James Lai, Synopsys, Inc.

Wednesday, April 15, 1:40 PM~5:00 PM Ballroom A
T6 ： Emerging Logic and Memory Technologies
Chair(s)： Albert Cheng, TSMC
Edward Chen, TSMC

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    1:40 PM~2:10 PM
    T6-1 Heterogeneous Integration of 2D Materials-Based Devices For New Memory-Centric Computing Architectures
    Voon Yew(Aaron) Thean, National University of Singapore
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    2:10 PM~2:40 PM
    T6-2 Next Generation Electronics Enabled by Growth-based Monolithic Integration of 2D Materials
    Jeehwan Kim, Massachusetts Institute of Technology(MIT)
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    2:40 PM~3:10 PM
    T6-3 Ultra-clean Interfaces on 2D Semiconductors for Energy Efficient Electronics
    Manish Chhowalla, University of Cambridge
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    3:30 PM~4:00 PM
    T6-4 Benchmarking the Gate Stack for Reliable 2D Materials Based Transistors
    Theresia Knobloch, TU Wien
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    4:00 PM~4:30 PM
    T6-5 MoS₂ and WSe₂ Transistors for Next-Generation Electronics
    Lain-Jong (Lance) Li, National University of Singapore
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    4:30 PM~5:00 PM
    T6-6 Breaking the Hydrogen Barrier: BEOL-Safe In₂O₃ Transistor
    Asif Khan, Georgia Institute of Technology

Wednesday, April 15, 3:40 PM~5:10 PM Ballroom C
D9 ： AI-assisted Chip Design
Chair(s)： Chien-Nan Liu
Taiwan Semiconductor Research Institute, NIAR
National Yang Ming Chiao Tung University

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    3:40 PM~4:10 PM
    D9-1 Pushing the Limits of Graph Learning for Scalable and Accurate Circuit Design
    Tsung-Yi Ho, The Chinese University of Hong Kong
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    4:10 PM~4:40 PM
    D9-2 Agentic AI for Chip Design
    Mark Ren, Agentrys
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    4:40 PM~5:10 PM
    D9-3 From Data to Design: ML Prediction for Digital and Analog Ics
    Jiang Hu, Texas A&M University

Thursday, April 16, 10:20 AM~11:50 AM Ballroom B
T10 ： Thermal Management and Materials for advanced CMOS and Packaging
Chair(s)： Andrew C. Kummel, University of California, San Diego

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    10:20 AM~10:50 AM
    T10-1 Thermal Challenges and the Future of Thermal Management in 3D Advanced Packaging Technologies
    Siddarth Krishnan, Applied Materials
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    10:50 AM~11:20 AM
    T10-2 Thermal Management with Polycrystalline Diamond
    Srabanti Chowdhury, Stanford University
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    11:20 AM~11:50 AM
    T10-3 Thermal Management Methods for Heterogeneous Integration
    Madhavan Swaminathan, Pennsylvania State University

Thursday, April 16, 10:20 AM~11:50 AM Ballroom C
D11 ： Intelligent Sensor Interface Circuits for Emerging Applications
Chair(s)： Yu-Te Liao, National Yang Ming Chiao Tung University

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    10:20 AM~10:50 AM
    D11-1 Building Neural Interfaces – Key Components, System Integration, and Technical Hurdles
    Minkyu Je, Korea Advanced Institute of Science and Technology (KAIST)
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    10:50 AM~11:20 AM
    D11-2 Recent Advances in Charge Amplifiers for Particle Detection
    Shiuh-Hua Wood Chiang, Brigham Young University
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    11:20 AM~11:50 AM
    D11-3 PLL-XO Codesign for Energy-Efficient and Ultra-Low Noise Frequency Synthesis
    Tawkang Jang, ETH Zürich

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