DAT Best Paper Award
Starting 2009, an Award Committee is formed for the selection of the Best Paper Award each year. The selection criteria of the award include the technical contents and writing quality of the paper as well as the quality of the presentation at the symposium. The award will be presented to the selected paper in the following year's symposium.
DAT Best Paper Award Committee
Led by the DAT Program Chairs, Prof. Kenichi Okada, Prof. Tai-Cheng Lee and Mr. Juin-Ming Luh, the award committee members consist of subcommittee co-chairs. The Award Committee will select the 2026 DAT Best Paper Award based on the criteria including the technical contents and depth, quality of the paper as well as the quality of the presentation. The award will be announced after the conference and granted in the International VLSI Symposium on Technology, Systems and Applications opening ceremony in 2027. The winner will be rewarded by a certificate and US$500 . Besides, it will also offer the registration fee waived of 2027 International VLSI Symposium on Technology, Systems and Applications.
2025 DAT Best Paper Award Winner ~ Congratulations!
The 2025 DAT Best Paper Award will be granted in International VLSI Symposium on Technology, Systems and Applications opening ceremony in 2026 and the winner will be rewarded by a certificate and US$500. Besides, it will also offer the registration fee waived of 2026 International VLSI Symposium on Technology, Systems and Applications.
• An 84.8-dB SNDR 62.5-kHz Bandwidth 2nd-order Noise-Shaping SAR ADC with a Duty-Cycled OTA Sharing Technique
Co-authors: Yu-Hsiang Wang, Yu-Gang Yeh and Tsung-Hsien Lin, National Taiwan University
• Overflow-Aware Via Placement for Dense Die-to-Die Connections in Advanced Package Routing
Co-authors: Hsin-Tzu Chang1, Wen-Hao Liu2, Iris Hui-Ru Jiang1, Zi-Sheng Lin3, Yueh-Hsin Tu3 and
Bing-Xun Song3
1 National Taiwan University
2 NVIDIA
3 Cadence Design Systems Inc.
2026 DAT Best Paper Award Candidates
• D1-1 An 88.1TOPS/W Hidden-neural-network Processor for Anomalous Sound Detection
Co-authors: Li-Yuan Chang, Ren-Hao Chiou, Heng-Siang Gao and Chia-Hsiang Yang
National Taiwan University
• D2-1 GNN-augmented MaskPlace: Fast Convergence in Macro Placement through Metaheuristic-synthesized Datasets
Co-authors: Varad Bharadiya, Krutik Patel, Madhav Rao, Shannon Muthanna and Chirag M. V.
International Institute of Information Technology, Bangalore (IIIT-Bangalore)
• D2-3 HAWK: Machine Learning-driven Waiver of Marginal Hold-time Violations withProcess-variation Awareness
Co-authors: Umang Singadiya, Pooja Beniwal and Sneh Saurabh
Indraprastha Institute of Information Technology, Delhi (IIIT-Delhi)
• D3-1 Training Approximate CNNs Using Block-wise Quadratic Surrogate Gradient
Co-authors: Ke Ma1, Tao Zhuang1, Shinichi Nishizawa2 and Shinji Kimura1
1 Waseda University
2 Hiroshima University
• D6-1 A 20 Gb/s 2VDD PAM-4 TX Output Driver with Core-only Devices
Co-authors: Che-Chia Tien and Tai-Cheng Lee
National Taiwan University
• D7-5 HLS Driven Obfuscation of DSP Hardware IP Designs Using Non Invertible Arbitrary Function and Reconfigurable Intertwined Obfuscation Logic
Co-authors: Anirban Sengupta, Nabendu Bhui, Vishal Chourasia and Ayush Kumar Singh
Indian Institute of Technology Indore (IIT Indore)
• D8-4 Precharge-free Non-volatile TCAM Using VCMA-MTJs with Op-amp-based Sensing and Embedded PUF Functionality
Co-authors: Kevin Vicuña 1, Marco Villegas2 and Lionel Trojman3
1 University of Calabria
2 Universidad San Francisco de Quito (USFQ)
3 Institut Supérieur d’Electronique de Paris (ISEP)