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Tuesday, April 22, 12:50 PM~5:30 PM Ballroom D
T1 ： Poster Session

  • T1-1 Highly Enhanced Endurance in Oxygen-Deficient Orthorhombic HfO2-x Film with Hole Doping
    Jinchen Wei, Zhirong Peng and Mansun Chan, The Hong Kong University of Science and Technology
  • T1-2 Restoration of Cu Grain Structure after Chemical Mechanical Polishing For Advanced 3D Integration
    Cheng-Hsuan Kuo1, Jit Dutta1, Dipayan Pal1, Madison Manley2, Rohan Sahay2, Danish Baig2,
    Muhannad Bakir2 and Andrew C. Kummel1
    1 University of California, San Diego
    2 EMD Electronics
  • T1-3 Tri-gate Normally-Off Power MIS-HEMT with Different Fin Configuration and Ferroelectric Charge Storage Gate Stack
    Rahul Rai1,2, Duy Hung Tran1, Quoc Khanh Nguyen1 and Edward-Yi Chang1
    1 National Yang-Ming Chiao Tung University
    2 Indian Institute of Technology, Kanpur
  • T1-4 Dependence of N-Well Guard Ring Bias on Latch-up Failure Level in a HV/LV Mixed-Voltage CMOS IC
    Chieh-Chen Ker1, Chen-Wei Hsu1, Chun-Yu Lin1, Ming-Dou Ker1, Chun-Chi Wang2 and
    Tsung-Yin Chiang2
    1 National Yang Ming Chiao Tung University
    2 Elan Microelectronics Corp.
  • T1-5 Impact of High-k Passivation Layers on the Electrical Stability of p-GaN Gate HEMTs
    Sheng-Kai Chen1, Zih-Jyun Hong1, Po-Tsung Tu2, Hui-Yu Chen2, Chang-Yan Hsieh2 ,De Shieh2,
    Po-Chun Yeh2, Shyh-Shyuan Sheu2, Wei-Chung Lo2, Shih-Chieh Chang2, Chang-Hong Shen 3 and Jen-Inn Chyi1
    1 National Central University
    2 Industrial Technology Research Institute
    3 Taiwan Semiconductor Research Institute
  • T1-6 Heat Dissipation Through Thermal Rail Insertion in Face-to-Face 2 Layer Stacked 6T CFET SRAM
    Bo-Hsun Juan, Liang-Chi Huang, Xiang-Ting Huang and Tzu-Hsuan Chang, National Taiwan University
  • T1-7 High Performance BEOL-compatible Amorphous Oxide Semiconductor Thin Film Transistor by Gate Insulator Improvement
    Tsung-Che Chiang1, Chen-Kai Hsu1, Yi-De Tsai1, Zhen-Hao Li1, Yu-Chen Chen1, Ming-Hsuan Ho2, Po-Chun Yeh2 and Po-Tsun Liu1
    1 National Yang Ming Chiao Tung University
    2 Industrial Technology Research Institute
  • T1-8 Scalability Assessment of BEOL FeFETs for Memory Applications
    Lung-En Chang and Pin Su, National Yang Ming Chiao Tung University
  • T1-9 Improved Delay and Inverter Performance of Negative Capacitance Bulk Junctionless Transistors
    Ruma S R and Manish Gupta, Birla Institute of Technology and Science, Pilani
  • T1-10 Impact on Dynamic Switching Performance for SiC MOSFETs with Current Spreading Layer
    Shih-Chiang Shen, Hua-Mao Chen, Chih-Hung Yen, Chih-Ming Lai, Yu-Jen Chen and Ju-Cheng Lin, Industrial Technology Research Institute
  • T1-11 Comparative Analysis of Electrical Characteristics of β-Ga₂O₃ Schottky and PN Diodes
    Ming-Yueh Huang1, Hua-Mao Chen1, Chih-Hung Yen1, Chih-Ming Lai1, Chin-Ya Tsai1, Shu-Yu Yao1, Shih-Chiang Shen1, Bich-Ngoc Chu3 and Tian-Li Wu3
    1 Industrial Technology Research Institute
    2 Taiwan Semiconductor Research Institute
    3 National National Yang Ming Chiao Tung University
  • T1-12 Optimizing 3.3kV Floating Guard Ring Structures in SiC Power Devices for Enhanced Breakdown Voltage
    Chia-Lung Hung, Yi-Kai Hsiao and Hao-Chung Kuo, Hon Hai Research Institute
  • T1-13 Amorphous Lanthanum Oxyhalide as possible high K Gate Dielectric
    John Robertson1, Ruyue Cao1,2 and Yuzheng Guo3
    1 Cambridge University
    2 Chinese Academy of Sciences
    3 Wuhan University
  • T1-14 Performance Evaluation of 55nm SRAM Cell with Buried Power Rail and Backside Power Delivery Network
    Xiaonan Wu1,2, Yitao Ma1,2,3, Rongmei Chen4 and Yunlong Li1,2
    1 Zhejiang University
    2 Zhejiang ICsprout Semiconductor Co., Ltd
    3 ZJU-Hangzhou Global Scientific and Technological Innovation Center
    4 Peking University
  • T1-15 Analysis of Low-Temperature Synthesized Graphene
    Yi-Hsiang Shih, Peng-Chi Wang, Yi-Cheng Huang and Wei-Chen Tu, National Cheng Kung University
  • T1-16 Abnormal On-Current Degradation Behavior in LDMOS Devices with Variant Positions of Contact Field Plate
    Kui-You Shao, Ting-Chang Chang, Wei-Chieh Hung and Hung-Ming Kuo, National Sun Yat-sen University

Tuesday, April 22, 1:40 PM~3:00 PM Ballroom A
T2 ： CMOS Memory and Cryo CMOS

  • 1:40 PM~2:00 PM
    T2-1 OTP-Generated Physical Unclonable Function for Hardware Security of AIoT Devices in Logic CMOS Platform
    M. Y. Lin, C. W. Liang, Y. K. Wang, P. H. Shih, J. C. Guo and Steve S. Chung, National Yang Ming Chiao Tung University
  • 2:00 PM~2:20 PM
    T2-2 Logic-Compatible Low-Voltage Complementary Analog Memory by CMOS FinFET Technology
    Hsin-Hung Yeh, Min-Hsun Chuang, Jiaw-Ren Shih, Chrong-Jung Lin and Ya-Chin King, National Tsing Hua University
  • 2:20 PM~2:40 PM
    T2-3 Experimental Characterization of Dopant Freeze-out Effect Enhanced Electrical Variability in Cryogenic 16-nm Complementary FinFETs
    Jia Zhe Ao1, Rui Qi Lin2, Pin Jie Pu2, Chen Yan Lin2, E Ray Hsieh2, Chien-Nan Kuo3 and Pei-wen Li3
    1 National Tsing Hua University
    2 National Central University
    3 National Yang Ming Chiao Tung University
  • 2:40 PM~3:00 PM
    T2-4 Enhanced Self-Heating and Reduced Thermal Conduction to Adjacent Devices at Cryogenic Temperatures with 200 nm SOI MOSFETs
    Kosuke Hatta1, Takayuki Mori1, Takahiro Mori2, Hiroshi Oka2 and Jiro Ida1
    1 Kanazawa Institute of Technology
    2 National Institute of Advanced Industrial Science and Technology

Tuesday, April 22, 1:40 PM~3:00 PM Ballroom C
D1 ： High-Speed Analog and RF

  • 1:40 PM~2:00 PM
    D1-1 A 4∼20-Gb/s Bit-Error-Rate Tester (BERT) Chiplet in 40-nm CMOS
    Guei-Lian Hsieh1, Yuan-Hsien Chen1, Yi-Ming Tsai1, Pen-Jui Peng1, Wei-Yan Chen2, Chih-Cheng Lu2 and Kai-Hsiang Chuang2
    1 National Tsing Hua University
    2 Industrial Technology Research Institute
  • 2:00 PM~2:20 PM
    D1-2 A Type-I PLL With Foreground Unity-Gain Bandwidth Calibration
    Yu-Chi Yen and Shen-Iuan Liu, National Taiwan University
  • 2:20 PM~2:40 PM
    D1-3 A D-Band IQ Sub-Harmonic Up-Conversion Mixer in 65-nm CMOS Process
    Chung-Yao Lu1, Yunshan Wang1, Chih-Kuang Lu1, Cheng-Han Wu1, Chau-Ching Chiong2 and
    Huei Wang1
    1 National Taiwan University
    2 Academia Sinica
  • 2:40 PM~3:00 PM
    D1-4 A 22FDX® Device and Balun Co-Optimized PA achieving 23dBm Psat, 34.9% peak PAE, 19.5% 6dB-PBO PAE and 20.6dB gain at 28GHz for 5G application
    Mingcheng Chang, Tom Herrmman, Clarissa Prawoto, Zaid Al-Husseini, Shafi Syed and
    Andreas Knorr, Globalfoundries

Tuesday, April 22, 1:40 PM~3:00 PM Mezzanine A+B
D2 ： AI Hardware Accelerator

  • 1:40 PM~2:00 PM
    D2-1 A Low-cost Reconfigurable Architecture for Efficient Softmax and GELU in Transformers
    Qi-Xian Wu1 , Shu-Sian Teng1 , Ming-Der Shieh1 , Chih-Tsun Huang2 and Juin-Ming Lu3
    1 National Cheng Kung University
    2 National Tsing Hua University
    3 Industrial Technology Research Institute
  • 2:00 PM~2:20 PM
    D2-2 SAVE: Systolic Array-based Accelerator for Vision Transformer with Efficient Tiling Strategy
    Yu-Chi Wu, Chih-Hung Kuo and Che-Wei Tsui, National Cheng Kung University
  • 2:20 PM~2:40 PM
    D2-3 CORA: Improving Computational Throughput in Compressor-Based MAC Designs via Carry-Out Replaced Multiply-Accumulator
    Li-Ling Tang, Yu-Guang Chen and Jing-Yang Jou, National Central University
  • 2:40 PM~3:00 PM
    D2-4 Energy-Efficiency Pipelined Architecture Design for RRAM-Based Digital Computing-in-Memory Applications
    Cheng-Han Yu1, Katherine Shu-Min Li1, Chun-Lung Hsu2 and Sying-Jyan Wang3
    1 National Sun Yat-sen University
    2 National Central University
    3 National Chung Hsing University

Tuesday, April 22, 3:30 PM~4:50 PM Ballroom C
D3 ： ADC and Power Management

  • 3:30 PM~3:50 PM
    D3-1 An 84.8-dB SNDR 62.5-kHz Bandwidth 2nd-order Noise-Shaping SAR ADC with a Duty-Cycled OTA Sharing Technique
    Yu-Hsiang Wang, Yu-Gang Yeh and Tsung-Hsien Lin, National Taiwan University
  • 3:50 PM~4:10 PM
    D3-2 A 10-MHz BW 70.3-dB SNDR Continuous-Time ΔΣ Modulator with PI Integrator for Frequency Modulated Continuous Wave Systems
    Ching-Cheng Wang, Ching-Ju Lu and Chia-Hung Chen, National Yang Ming Chiao Tung University
  • 4:10 PM~4:30 PM
    D3-3 A Buck-Boost Converter with Duty-Cycle and Dynamic Slope Compensation Techniques for Output Ripple Reduction
    Hong-Wei Chu1, Ying-Yu Yang1, Kwan-Jen Chu2, Jung-Sheng Chen2, Hao-Yi Guo2 and Yu-Te Liao1
    1 National Yang Ming Chiao Tung University
    2 Richtek Technology Corporation
  • 4:30 PM~4:50 PM
    D3-4 Adaptively Skewed Gate Driver Integrated Circuit for SiC MOSFETs to Reduce Switching Loss
    Jian-Bang Hou1, Chung-Hsun Huang2 and Jia-Hui Wang3
    1 National Chung Cheng University
    2 National Cheng Kung University
    3 Himax Technologies, Inc.

Tuesday, April 22, 3:30 PM~4:50 PM Mezzanine A+B
D4 ： Efficient Signal Processing Circuit Design

  • 3:30 PM~3:50 PM
    D4-1 An Energy Efficient 64-2048-Point FFT Computation Chip for EEG Signal Processing
    Jingbin Mai1, WeiWei Shi1, Suixing Zhuang1 and Yida Yuan2
    1 Shenzhen University
    2 WingSemi Technology
  • 3:50 PM~4:10 PM
    D4-2 A Power-Area Efficient Approximate Multiplier Based on Piecewise-Plane-Fitting
    Jiasheng Wu, Weiwei Shi, Haoren Qin, Kaifu Feng and Siyi Li, Shenzhen University
  • 4:10 PM~4:30 PM
    D4-3 Sliding-Window-based Fast and Lightweight ADC Pseudo-Randomness Compensation Technique for Low-Cost ADC
    Jisu Kwon and Daejin Park, Kyungpook National University
  • 4:30 PM~4:50 PM
    D4-4 Accelerating Polynomial Multiplication Using a Three-Stage NTT with Radix-2 Butterfly Unit
    Ramyavani P, Archith Casheekar, Tanay Reddy, Subhendu Kumar Sahoo, G Geetha Kumari and
    Amit Kumar Panda, BITS-Pilani, Hyderabad Campus

Wednesday, April 23, 10:20 AM~11:40 AM Ballroom A
T4 ： Modeling of Leading Edge Node of CMOS

  • 10:20 AM~10:40 AM
    T4-1 Cross-Layer Modeling of Self-Heating Coupled Reliability with Back Side Power Delivery Network
    Yu Li, Cong Shen, Sihao Chen, Runsheng Wang and Lining Zhang, Peking University
  • 10:40 AM~11:00 AM
    T4-2 Modeling and Simulation of Intrinsic Gate Capacitance in Ultrathin Body Nanosheets Including Quantum Effects
    Ching-Wang Yao, Tzu-Yun Liu, Tao Chou, Hsin-Cheng Lin and C. W. Liu, National Taiwan University
  • 11:00 AM~11:20 AM
    T4-3 Ultra-scale (0.014 μm2) High-efficient 10A 6T CFET-SRAM Cells Combined Backside Power Deliver Networks and Backside Bit-lines
    Yu Cheng Chen1, Li An Yu1, Kai Wen Cheng2 and E Ray Hsieh1
    1 National Central University
    2 National Tsing Hua University
  • 11:20 AM~11:40 AM
    T4-4 Unveiling the Potential of Nanosheet and Complementary FET with MFIS and MFMIS Ferroelectric Negative-Capacitance Gate Stack
    Sandeep Semwal and Pin Su, National Yang Ming Chiao Tung University

Wednesday, April 23, 10:20 AM~11:40 AM Ballroom C
T6 ： FeFET Devices and Applications

  • 10:20 AM~10:40 AM
    T6-1 Superlattice HfZrO2 Ultra-Thin Poly-Si Channel (3.5 nm) Junctionless 1T FeTFTs Featuring Nearly Zero Memory Window Degradation Rate (2.8%) and Robust 10 K to 423 K Retention for 3-D NAND NVMs and Neuromorphic Systems
    Dong-Ru Hsieh1, Zi-Yang Hong1, Huai-En Luo1, Li-Ting Chou1, Wei-Ju Yeh1, Jia-Chian Ni1,
    Shang-Lin Hsieh1, Ciao-Fen Chen1,2, Yen-Fu Lin2, Shun-Tsung Lo1 and Tien-Sheng Chao1
    1 National Yang Ming Chiao Tung University
    2 National Chung Hsing University
  • 10:40 AM~11:00 AM
    T6-2 28nm Ferroelectric Field Effect Transistor Based Associative Memory Array for Few-Shot Learning and Genome Analysis
    Alptekin Vardar1, Nellie Laleni1, Mengyuan Li2, Mohammad Mehdi Sharifi2, Marcel Günter1,
    Franz Müller1, Yu Qian2, Cheng Zhuo3, Xunzhao Yin3, Michael Niemier2, X. Sharon Hu2,
    Konrad Seidel1, Kai Ni2 and Thomas Kämpfe1
    1 Fraunhofer IPMS
    2 University of Notre Dame
    3 Zhejiang University
  • 11:00 AM~11:20 AM
    T6-3 Enhancing Analog Performance in Ferroelectric Synapses via Independent Double-Gate Nanosheet FeFETs
    F. Wu1, C.-Y. Chiu1, C.-H. Wu2, V. P.-H. Hu2, P. Su1 and C.-J. Su1,3
    1 National Yang Ming Chiao Tung University
    2 National Taiwan University
    3 Taiwan Semiconductor Research Institute
  • 11:20 AM~11:40 AM
    T6-4 Investigation of the Gate Dimension Influences on Performance and Reliability of Silicon-Doped Hafnium Oxide (HSO) FeFETs
    Ivan Kuznietsov1, Hsien-Yang Liu1, Yannick Raffel2, Thomas Kämpfe2,3, Konrad Seidel2,
    Maximilian Lederer2 and Tian-Li Wu1
    1 National Yang Ming Chiao Tung University
    2 Fraunhofer IPMS
    3 Technische Universität Braunschweig

Wednesday, April 23, 10:20 AM~11:20 AM Mezzanine A+B
D6 ： System Security, Memory, and ECO Design

  • 10:20 AM~10:40 AM
    D6-1 Address-Dependent Divided-Bit-Line NAND Flash Memory for Reduction in Latency and Energy
    Yuta Sugisawa1 and Toru Tanzawa2
    1 Shizuoka University
    2 Waseda University
  • 10:40 AM~11:00 AM
    D6-2 Spectre Attack Detection with Formal Method on RISC-V Processor at RTL Design Level
    Chih-Cheng Ting1, Yu-Ting Huang1, Yu-Tung Chen1, Yean-Ru Chen1 and En-Hsiang Lin2
    1 National Cheng Kung University
    2 Realtek Semiconductor Corp.

  • 11:00 AM~11:20 AM
    D6-3 Multi-well ECO Fabric Base Standard Cell to Enable Power Domain Crossings
    R Reshma Krishnakumar, Puneet Shah, Suhas Gourimath and Ramanath Dharmavaram
    NXP Semiconductors

Wednesday, April 23, 1:40 PM~3:00 PM Ballroom C
D7 ： Hardware Friendly Model Optimization for Compute Intensive Applications

  • 1:40 PM~2:00 PM
    D7-1 Mixed-Precision Computing for the Denoising Diffusion Implicit Models by Trainable Thresholds
    Tsung-Lin Tsai, Yi-Cheng Lo and An-Yeu (Andy) Wu, National Taiwan University
  • 2:00 PM~2:20 PM
    D7-2 Training and Optimization of Spiking Transformer Models under ReRAM Non-Ideal Effects
    Chih-Yu Hsu, Tsu-Hsiang Chen, Chih-Tsun Huang and Jing-Jia Liou, National Tsing Hua University
  • 2:20 PM~2:40 PM
    D7-3 Constrained Bi-Objective Pruning Framework for Ultra-Low Latency ML Inference on FPGAs
    Chi-Jui Chen1, Daniel Chen2, Jia-Hong Lai2, Po-Jen Lai1, Wei-Hsuan Hung1 and Bo-Cheng Lai1
    1 National Yang Ming Chiao Tung University
    2 Kaohsiung American School
  • 2:40 PM~3:00 PM
    D7-4 Reconfigurable and Hardware-Efficient KECCAK Architecture with SHAKE Integration and Dynamic Input Processing for Post Quantum Cryptography
    Sahil Chauhan and Rahul Shrestha, Indian Institute of Technology Mandi

Wednesday, April 23, 1:40 PM~3:00 PM Ballroom D
D8 ： Advances in Physical Design for Chips and Packages

  • 1:40 PM~2:00 PM
    D8-1 Efficient Chip-Level Global Router: ICCAD 2024 CAD Contest Problem D
    ShaoChien Lu, YuCheng Lin, MingYi Huang, YiChia Wu and RungBin Lin, Yuan Ze University
  • 2:00 PM~2:20 PM
    D8-2 A Detailed-Routability-Driven 3D Global Router Using Soft Demand and Pin Map Factor
    Tzu-Chieh Ni, Po-Yu Lin and Yih-Lang Li, National Yang Ming Chiao Tung University
  • 2:20 PM~2:40 PM
    D8-3 River Segments Detection Strategy for Advanced Packages Routing
    Chun-I Li1, Wen-Hao Liu2 and Tsung-Yi Ho3
    1 Synopsys
    2 NVIDIA
    3 The Chinese University of Hong Kong
  • 2:40 PM~3:00 PM
    D8-4 Overflow-Aware Via Placement for Dense Die-to-Die Connections in Advanced Package Routing
    Hsin-Tzu Chang1, Wen-Hao Liu2, Iris Hui-Ru Jiang1, Zi-Sheng Lin3, Yueh-Hsin Tu3 and
    Bing-Xun Song3
    1 National Taiwan University
    2 NVIDIA
    3 Cadence Design Systems Inc.

Wednesday, April 23, 1:40 PM~3:00 PM Mezzanine A+B
T8 ： Magnetic Devices and Applications

  • 1:40 PM~2:00 PM
    T8-1 From MRAM to SP-MTJ: An Ultrathin Mo Insertion in Magnetic Tunnel Junction-based P-bits for Solving Combinatorial Optimization Problem
    Yu-Hsuan Lin1, Ching Shih1,2, Ming-Chun Hong1,2, Chen-Yu Yang1,2, Guan-Long Chen2,
    Hsin-Han Lee2, Yu-Chen Hsin2, Chiao-Yun Lo2, Sin-You Huang2, Ting-Syun Huang1, Cheng-Yi Shih2,
    Shan-Yi Yang2, I-Jung Wang2, Yao-Jen Chang2, Shih-Ching Chiu2, Yi-Hui Su2, Chih-Yao Wang2,
    Kuan-Ming Chen2, Ho-Lin Tsai2, Jeng-Hua Wei2, Shyh-Shyuan Sheu2, Wei-Chung Lo2,
    Shih-Chieh Chang2 and Tuo-Hung Hou1
    1 National Yang Ming Chiao Tung University
    2 Industrial Technology Research Institute
  • 2:00 PM~2:20 PM
    T8-2 Improved STT Efficiency with Ultrathin Magnesium Composite Free Layer for Energy-Efficient MRAM
    Tsai-Yu Wu1, Chen-Yu Yang1,2, Yu-Ho Kao1, Ming-Chun Hong1,2, Guan-Long Chen2, Hsin-Han Lee2, Yu-Chen Hsin2, Chiao-Yun Lo2, Sin-You Huang2, Yu-Tong Zhan1, Cheng-Yi Shih2, Shan-Yi Yang2,
    I-Jung Wang2, Yao-Jen Chang2, Shih-Ching Chiu2, Yi-Hui Su2, Chih-Yao Wang2, Kuan-Ming Chen2, Jeng-Hua Wei2, Shyh-Shyuan Sheu2, Wei-Chung Lo2, Shih-Chieh Chang2 and Tuo-Hung Hou1
    1 National Yang Ming Chiao Tung University
    2 Industrial Technology Research Institute
  • 2:20 PM~2:40 PM
    T8-3 A 2-Bit 4T2MTJ MRAM Bit-Cell for Compute-in-Memory Applications
    Zhengde Xu1,2, Wei Zhang2, Jianze Wang2, Xiaoyan Zhang2, Yunuo Cen2, Xue Zhang1,
    Xuanyao Fong2 and Zhifeng Zhu1,3
    1 ShanghaiTech University
    2 National University of Singapore
    3 Shanghai Engineering Research Center of Energy Efficient and Custom AI IC
  • 2:40 PM~3:00 PM
    T8-4 Magnetic Shift Register with Self-Differential Sensing Method
    Y. Ueda, M. Quinsat, N. Shimomura, S. Hashimoto, N. Umetsu, Y. Ootera, J. Iwata, T. Kondo,
    M. Kado and S. Miyano, KIOXIA Corporation

Wednesday, April 23, 3:30 PM~4:50 PM Ballroom D
D10 ： Design and Test of Systems in Advanced Technology

  • 3:30 PM~3:50 PM
    D10-1 Hybrid Structured Clock Network Construction with GPUs for Large Designs
    Wen-Hao Liu, Hsin-Tzu Chang, Anthony Agnesina, Rongjian Liang, Anand Rajaram and
    Haoxing Ren, NVIDIA
  • 3:50 PM~4:10 PM
    D10-2 Stabilizer-Based Dynamic Assertion Circuits (SBDACs) for Quantum Circuits
    Cheng-Yuan Lin, Ji-Qing Yan and Yean-Ru Chen, National Cheng Kung University
  • 4:10 PM~4:30 PM
    D10-3 Repair and Timing-Aware Signal Path Assignment for Inter-Die Interconnects
    Guan-Sheng Chen1, Po-Jen Yen1, Knuth Lu2, Chung-Ching Peng2, Yi-Shing Chang2 and
    Jiun-Lang Huang1
    1 National Taiwan University
    2 Intel Corporation
  • 4:30 PM~4:50 PM
    D10-4 Behavioral Model Compiler for Simulating Read Disturbances and Read/Write Errors in STT-MRAMs
    Yun-Ting Chuan1, Liang-Ying Su1, Shih-Hsu Huang1 and Jin-Fu Li2
    1 Chung Yuan Christian University
    2 National Central University

Wednesday, April 23, 3:20 PM~5:00 PM Mezzanine A+B
T9 ： Heterogeneous Devices and Integration

  • 3:20 PM~3:40 PM
    T9-1 An Innovative Programmable Packaging for AIoT Application
    Ching-Iang Li, Yung-Sheng Chang, Siou-Zih Lin, Jie Zhang, Chao-Kai Hsu, Tsung-Yi Hung,
    Tsung-Yu Ou Yang, Feng-Hsiang Lo, Chin-Hung Wang and Wei-Chung Lo,
    Industrial Technology Research Institute
  • 3:40 PM~4:00 PM
    T9-2 A Study of Bit Revival Operation for Logic Compatible Twin-bit RRAM in FinFET Technologies
    Ting Kan, Kai-Ching Chuang, Bing-Rong Tang, Jiaw-Ren Shih, Chrong-Jung Lin and Ya-Chin King, National Tsing Hua University
  • 4:00 PM~4:20 PM
    T9-3 Design and Optimization of Ge PINIP Photodetectors for Enhanced Responsivity and Bandwidth in Ultrafast Photonic Applications
    Avishek Das, Logeshwaran Venkatesapandian, Gwangjin Bak and C. W. Liu, National Taiwan University
  • 4:20 PM~4:40 PM
    T9-4 A 90-110GHz Cascode Amplifier for High Gain and Wideband
    Jinq-Min Lin, Adhi Cahyo Wijaya and Jyh-Chyurn Guo, National Yang Ming Chiao Tung University
  • 4:40 PM~5:00 PM
    T9-5 Formation of Cu Nodule Defects and Their Impact on the Electrical Properties of RDL
    Su-Ching Hsiao1, Wei-Lan Chiu1, Chia-Chang Shih2, Hsiang-Hung Chang1, Chin-Hung Wang1 and Wei-Chung Lo1
    1 Industrial Technology Research Institute
    2 Materials Analysis Technology Inc.

Thursday, April 24, 10:20 AM~11:20 AM Ballroom A
T10 ： Modules for 2D Channel FET

  • 10:20 AM~10:40 AM
    T10-1 Atomic Layer Epitaxial 2D Dielectric h-AlN as Interfacial Layer with Excellent Leakage and EOT < 1 nm for TMD-FETs
    Shin-Yuan Wang 1, Yu-Chin Lin 1, Yu-Che Huang 1, Chenming Hu 1,2 and Chao-Hsin Chien1
    1 National Yang Ming Chiao Tung University
    2 University of California
  • 10:40 AM~11:00 AM
    T10-2 Synthesis of NbS2 via H2S Annealing of Nb and Its Application as a Contact Material in WSe2 pFETs
    Koki Hori1,2, Wen Hsin Chang1, Toshifumi Irisawa1, Atsushi Ogura2 and Naoya Okada1
    1 National Institute of Advanced Industrial Science and Technology (AIST)
    2 Meiji University
  • 11:00 AM~11:20 AM
    T10-3 Scalable Fabrication of High-Performance Short-Channel CVD MoS2 MOSFETs with Scaled Dielectric Using a Metal-Bridging Free Approach
    Yuan-Chun Su1, Yun-Cheng Chang1, Jian-Chen Tsai1, Chun-Jung Su1, Pei-Wen Li1,
    Wen-Hao Chang1,2 and Horng-Chih Lin1
    1 National Yang Ming Chiao Tung University
    2 Academia Sinica

Thursday, April 24, 10:20 AM~12:00 PM Mezzanine A+B
T12 ： Wide Bandgap Devices for Power and RF

  • 10:20 AM~10:40 AM
    T12-1 Investigations of Temperature Dependent Performances in Lateral β-Ga2O3 MOSFETs
    Bich-Ngoc Chu1, Tiffany Huang1, Ta-Shun Chou2, Saud Bin Anoo2, Andreas Popp2,
    Hao-Chung Kuo3,4, Chang-Ching Tu5 and Tian-Li Wu1
    1 National Yang Ming Chiao Tung University
    2 Leibniz-Institut für Kristallzüchtung (IKZ)
    3 National Yang Ming Chiao Tung University
    4 Hon Hai Research Institute
    5 National Central University
  • 10:40 AM~11:00 AM
    T12-2 Investigation on Component-Level Surge Robustness of 4H-SiC 1700-V VDMOSFET
    Ya-Zhi Hu, Ming-Han Wang and Ming-Dou Ker, National Yang Ming Chiao Tung University
  • 11:00 AM~11:20 AM
    T12-3 A Symmetric 4H-SiC CMOS Inverter with Self-aligned PMOSFET Counter Doping
    Chuan-Han Chen1,Cheng-Shu Chang1, Haui-Lin Huang1, Chia-Yang Wang1, Chih-Ya Tsai2,
    Yu-Yuan Chen2, Hua-Mao Chen2, Chih-Hung Yen2 and Bing-Yue Tsui1
    1 National Yang Ming Chiao Tung University
    2 Industrial Technology Research Institute
  • 11:20 AM~11:40 AM
    T12-4 Investigations of H2+NO POA Treatment on Gate Breakdown and Stress-induced Interface States Density in 4H-SiC MOS Capacitors
    Wei-Cheng Lin1, Seokhuey Soo1, Gui-Hong Liu1, Yu-Jie Chiu1, Abdul Hannan Yeo2,
    Voo Qin Gui Roth2, Lakshmi Kanta Bera2, Navab Singh2, Umesh Chand2 and Tian-Li Wu1
    1 National Yang Ming Chiao Tung University
    2 Agency for Science, Technology and Research (A*STAR)
  • 11:40 AM~12:00 PM
    T12-5 High-Gain GaN IMPATT Diodes for mm-Wave Signal Generation
    Zhongtao Zhu1, Andy Xie2 and Patrick Fay1
    1 University of Notre Dame
    2 Qorvo

Thursday, April 24, 11:25 AM~12:45 PM Ballroom A
T13 ： Oxide Semiconductor Transistors

  • 11:25 AM~11:45 AM
    T13-1 Quantification of Contact-Doping Effect in Ultrathin In2O3 Transistors
    Jian-Yu Lin, Chang Niu, Zehao Lin, and Peide D. Ye, Purdue University
  • 11:45 AM~12:05 PM
    T13-2 Impact of Channel Thickness and Annealing Ambient on Electrical Characteristics of Ultrathin body AlOx-passivated InOx FETs
    Chia-Tsong Chen1, Kasidit Toprasertpong2, Toshifumi Irisawa1, Wen Hsin Chang1, Shinji Migita1, Yukinori Morita1, Hiroyuki Ota1 and Tatsuro Maeda1
    1 National Institute of Advanced Industrial Science and Technology
    2 The University of Tokyo
  • 12:05 PM~12:25 PM
    T13-3 Source/Drain Electrode Tuning for Self-Heating Mitigation in Double-Gate IGZO OSFET Using 12-inch IGZO-on-Si 3D Monolithic Integration
    Kuei-Fen Chang, C.-M. Yih, Shih-Chi Yen, Hung-Shen Pai, Jer-Chen Chang, Chia-Ming Wu,
    Jyun-Hong Shih, Yung-Lung Hsu, Hiroshi Yoshida, Lingyen Yeh, Kuo-Hsiung Chen and
    Shou-Zen Chang, Powerchip Semiconductor Manufacturing Corporation
  • 12:25 PM~12:45 PM
    T13-4 Reliability Study of Self-Aligned Top-Gated a-IGZO TFTs by N2 and N2O Plasma Treatment
    Yuan-Ming Liu1, Hsien-Ming Sung1, Yu-Shan Wu1, Rong-Wei Ma1, Johannes Gracia1,
    Hidenari Fujiwara1, Tsang-Long Chen2, Cheng-Hsu Chou2 and C. W. Liu1
    1National Taiwan University
    2Innolux Corporation

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