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Tuesday, April 23, 12:50 PM~5:30 PM Ballroom D
T1 ： Poster Session

  • T1-1 A Simplified Method for RTN Assessment and Novel Understanding on AC RTN
    Chenyang Zhang1,2, Yu Xiao1,2,Yongkang Xue1,2, Da Wang1,2, Pengpeng Ren*1,2 and Zhigang Ji*1,2
    1National Key Laboratory of Science and Technology on Micro/Nano Fabrication, SJTU
    2Department of Micro/Nano Electronics, SJTU
  • T1-2 BEOL Layout Optimization to Improve RF Performance of 40nm Node Technology for High-Frequency Applications
    Avishek Das1, Hsin-Cheng Lin2, and C. W. Liu1,2
    1Graduate School of Advanced Technology, National Taiwan University
    2 Graduate Institute of Electronics Engineering, National Taiwan University
  • T1-3 A Study of Physical Unclonable Function by Dielectric Breakdown in High-κ Metal Gate Device
    Geng-Shiu Lin, Ya-Chin King, Chrong-Jung Lin, National Tsing Hua University
  • T1-4 Control of Hysteresis and Latch-up on Steep Switching “PN-Body Tied SOI-FET Diode” by Ar-Ion Implantation
    Hiroyoshi Matsushita, Takayuki Mori, Jiro Ida,
    Kanazawa Institute of Technology, Ishikawa
  • T1-5 Latch-up Risk in 5V-tolerant I/O Buffer Surrounded by NBL Isolation Ring with Low-Voltage Bias
    Chen-Wei Hsu1 and Ming-Dou Ker1,2
    1Institute of Pioneer Semiconductor Innovation, National Yang Ming Chiao Tung University
    2Institute of Electronics, National Yang Ming Chiao Tung University
  • T1-6 Triple Self-Aligned Split-Gate Architecture for High-Speed Applications of 4H-SiC VDMOSFETs
    Chia-Lung Hung1, Bing-Yue Tsui2, Yi-Kai Hsiao1, Hao-Chung Kuo1 1.
    1Semiconductor Research Center, Hon Hai Research Institute
    2Institute of Electronics, National Yang Ming Chiao Tung University
  • T1-7 Enhanced Charge Transfer Efficiency Using Ring Vertical Transfer Gates in Backside Illuminated CMOS Image Sensor
    Yu-Chieh Lee1, Avishek Das2, Yi Huang3, Logeshwaran Venkatesapandian2, C. W. Liu1,2,3
    1Graduate Institute of Electronics Engineering, National Taiwan University
    2Graduate School of Advanced Technology, National Taiwan University
    3Graduate Institute of Photonics and Optoelectronics, National Taiwan University
  • T1-8 Effects of Channel Thickness on DC/RF Performance of InAlGaN/AlN/GaN HEMTs
    De Shieh1, Zheng-fong Lee1, Ming-Yuan Lee1, Hui-Yu Chen2, Chang-Yan Hsieh2,Po-Tsung Tu2, Po-Chun Yeh2, Shyh-Shyuan Sheu2, Wei-Chung Lo2, Shih-Chieh Chang2, Chang-Hong Shen3, Jia-Min Shieh3, and Jen-Inn Chyi1
    1National Central University
    2Industrial Technology Research Institute
    3Taiwan Semiconductor Research Institute
  • T1-9 Extremely High Noise Margin and Low Leakage in ULP Circuits with NCFETs
    Sandeep Semwal1, Rohit Kumar Nirala1, Manish Gupta2, and Abhinav Kranti1
    1 Low Power Nanoelectronics Research Group, Department of Electrical Engineering, IIT Indore
    2Department of Electrical & Electronics Engineering, BITS Pilani KK Birla Goa Campus
  • T1-10 Impact of In and Ga Fractions in Lattice-Matched InAlGaN Barrier Layer on Performance of InAlGaN/GaN MISHEMT
    Catherine Langpoklakpamaa, Yi-Kai Hsiaob, Chun-Hsiung Linc, Edward Yi Changcd, Hao-Chung Kuoa
    aDepartment of Photonics and Institute of Electro-Optical Engineering, College of Electrical and Computer Engineering, National Yang-Ming Chiao Tung University
    bHon Hai Research Institute, Semiconductor Research Center, cInternational College of Semiconductor Technology, National Yang-Ming Chiao Tung University
    dDepartment of Materials Science and Engineering, National Yang-Ming Chiao Tung University
  • T1-11 The Study of Normally-on Power GaN HEMTs in QST Substrate with High Breakdown Voltage
    Pei-Tien Chen1, Chia-Hao Chuang1, An-Chen Liu1, and Hao-Chung Kuo1, 2, Fellow, IEEE
    1Department of Photonics and Institute of Electro-Optical Engineering, National Yang Ming Chiao Tung University
    2Semiconductor Research Center, Hon Hai Research Institute
  • T1-12 Lattice Scattering Related Flicker Noise in Silicon-doped Hafnium Oxide FeFETs
    Daniel Hessler, Ricardo Olivo, Konrad Seidel, Raik Hoffmann, Sourav De, Yannick Raffel Fraunhofer IPMS, Center Nanoelectronic Technologies (CNT), Dresden
  • T1-13 Co metal ALD on Cu with Cyclic clean by Peroxide and Hydrazine for Inverse Hybrid Metal Bonding
    Cheng-Hsuan Kuo1, Dipayan Pal2, Victor Wang1, Madison Manley4, Rohan Sahay4, Ravindra Kanjolia3, Mansour Moinpour3, Jacob Woodruff3,Bakir Muhannad4, Jeff Spiegelman5, Andrew C. Kummel2
    1Materials Science and Engineering Program, University of California
    2Department of Chemistry and Biochemistry, University of California
  • T1-14 High Thermally Conductive, High-Speed Deposition of AlN by Bipolar High Power Impulse Magnetron Sputtering
    Ping Che Lee1 , Aaron J. McLeod2 , Mingeun Choi3 , Diego Vaca3 , Diego Contreras Mora1 Satish Kumar3, Andrew C. Kummel1
    1Materials Science and Engineering Program, University of California
    2Department of Chemistry and Biochemistry, University of California
  • T1-15 Study of frequency capability of 1.7kV SiC MOSFET with current spreading layer
    Hua-Mao Chen1, Shih-Chiang Shen1, Chih-Hung Yen1, Yu-Ting Chen2, Chih-Ming Lai1, Shin-Yi Huang1, Chin-Ya Tsai1
    1Electronic and Optoelectronic System Research Laboratories, Industrial Technology Research Institute
    2National Applied Research Laboratories, Taiwan Semiconductor Research Institute
  • T1-16 Ultra-thin and High-quality Pt-Silicidation using CW Laser Annealing Process
    Seung Mo Kim1, Min Gyu Kwon2, Taekyu Woo1, Ki Sung Kim1, Yongsu Lee1, Hyeon Jun Hwang1, Joon Kim1,Byoung Hun Lee1 1Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology
    2School of Materials Science and Engineering, Gwangju Institute of Science and Technology
  • T1-17 Enhanced Reliability of Ultra-low-k Dielectric with Columnar Pores using hBN Capping Layer
    Mostafa Raafat Bakry Okasha, Mansun Chan, Department of ECE, The Hong Kong University of Science and Technology
  • T1-18 Improving NDR and RF Characteristics of InGaAs MOSFETs through Ferroelectric Thickness Tuning for Enhanced Energy Efficiency
    Mu-Yu Chen, Edward-Yi Chang, National Yang Ming Chiao Tung University
  • T1-19 Investigation of IGZO Thin Film Transistors with Copper Electrode under Varied Channel Lengths and Different Gate Insulator Annealing Temperatures
    Po-Yi Lee, Kuan-Ju Zhou, Yu-An Chen, Po-Yu Yen, Ting-Chang Chang, National Sun-Yat-Sen University
  • T1-20 Transient Responses of The Majority and Minority Carriers During Rapid Reduction of The Inversion Charges in an MOS Structure
    Sung-Wei Huang1 and Jenn-Gwo Hwu1,2
    1Graduate Institute of Electronics Engineering, National Taiwan University.
    2Department of Electrical Engineering, National Taiwan
      University
  • T1-21 A -40◦C to 125◦C, 1.12 ppm/◦C Multiple Voltage Bandgap Reference Circuit
    Raveesh Khola, Dr. Ambika Prasad Shah, Dr. Anup Shukla, Indian Institute of Technology Jammu
  • T1-22 Semiconductor Traceability: Die Annotations Patterning by Maskless Exposure Technology
    K. Varga1, T. Uhrmann1, R. Holly1, T. Zenger1, A. Spitzer1, F. Bögelsack1, S. Vanclooster2, M. Reybrouck2, D. Janssen2, N. Van Herck2, M. Vandevyvere2
    1EV Group, DI Erich Thallner Strasse 1, St. Florian am Inn 
    2Fujifilm Electronic Materials (Europe) N.V. Zwijndrecht

Tuesday, April 23, 1:40 PM~3:00 PM Ballroom A
T2 ： 3D Integration

  • 1:40 PM~2:00 PM
    T2-1 3D Architecture to Integrate Backside Power Interconnect and Integrated Passive Device for Thermal and Electrical Performance Management of Logic Chip
    C.-L. Lu1, S.-C. Lin1, C.-S. Ho1, H.-C. Lin1, M.-H. Chiu1, C.-H. Chuang1, M.-C. Lu1, W.-Y. Lai1, N. Basu2, Miller Liao2,
    and S.-Z. Chang1
    1R&D, Powerchip Semiconductor Manufacturing Corporation
    2Graduate School of Advanced Technology & Department of Mechanical Eng., National Taiwan University
  • 2:00 PM~2:20 PM
    T2-2 Low Temperature (250oC) and Fine Pitch (≤4μm) New Nanocrystalline Cu/SiO2Chip-on-Wafer Hybrid Bonding for 3D Chip Integration
    Ang-Ying Lin1, Yu-Min Lin1, Chun-Lin Lu2, Hsin-Yi Liao2, Chen-Chun Yu1, Ou-Hsiang Lee1, Tsung-Chieh Chiu1, Wei-Lan Chiu1, Hsiang-Hung Chang1, Shou-Zen Chang2
    1Industrial Technology Research Institute
    2Powerchip Semiconductor Manufacturing Corporation
  • 2:20 PM~2:40 PM
    T2-3 Advanced Chip on Wafer Hybrid Bonding with Copper/Polymer Base Adhesive
    Tsung-Yu Ouyang1, Yu-Min Lin1, Yu-Ping Chan1, Ou-Hsiang Lee1, Ching-Kuan Lee1, Hsiang-Hung Chang1, Chin-Hung Wang1, Wei-Chung Lo1, Po-Yao Chuang2, Ying-Chung Tseng2, Po-Hao Tsai2, Michael Gallagher3, Christopher Gilmore3
    1Industrial Technology Research Institute
    2DuPont Electronics and Industrial, Miaoli
    3DuPont Electronics and Industrial, Marlborough
  • 2:40 PM~3:00 PM
    T2-4 Si Multi-Bridge Channel CMOS Inverter with Five Stacked Layers Fabricated from Epitaxial Si0.8Ge0.2/Si Multilayers
    Wei-Yuan Chang1, Guang-Li Luo1*, Chun-Lin Chu1, Shih-Hong Chen1,Fu-Kuo Hsueh1, Bo-Yuan Chen1, Yao-Jen Lee2, and Wen-Fa Wu1
    1Taiwan Semiconductor Research Institute
    2Advanced Semiconductor Institute, National Yang Ming Chiao Tung University

Tuesday, April 23, 1:40 PM~3:00 PM Mezzanine A+B
T3 ： Memory for Computing

  • 1:40 PM~2:00 PM
    T3-1 An RRAM-Based 40.6 TOPS/W Energy-Efficient AI Inference Accelerator with Quad Neuromorphic-Processor-Unit for Highly Contrast Recognition
    Y. L. Lin1, Y. R. Liu1, T. C. Kao1, M. Y. Lee2, J. C. Guo1, T. –H. Hou1,2,Steve S. Chung1
    1National Yang Ming Chiao Tung University
    2Taiwan Semiconductor Research Institute
  • 2:00 PM~2:20 PM
    T3-2 Novel Strategies Toward High-performance FeFET for Computing In Memory Application
    Giuk Kim, Hyojun Choi, Sangho Lee, Hunbeom Shin, Lingwei Zhang, Sangmok Lee, Yunseok Nam, Woongjin Kim, Jihye Ock, Sujeong Lee, Hyunjun Kang, and Sanghun Jeon, Korea Advanced Institute of Science and Technology
  • 2:20 PM~2:40 PM
    T3-3 In-Memory-Computing and In-memory Cosine Similarity Search with Memory Diode Featuring Low Latency and High Energy Efficiency
    Xianggao Wang1,2,, Xiang Ding1, Shifan Gao1, Zhangsheng Lan1, Liang Zhao1, Wenhao Wu2, Yi Zhao1
    1Zhejiang University
    2China Nanhu Academy of Electronics and Information Technology
  • 2:40 PM~3:00 PM
    T3-4 A Self-Calibratable Spiking Neuron based on Dual-mode Memritor for High-Accuracy Spiking Neural Networks
    Jiajun Gao1, Linbo Shan1, Zongwei Wang1,2, Yintong Ji1, Chaoyi Ban1, Yabo Qin1, Yimao Cai1,2, Ru Huang1, 2
    1School of Integrated Circuits, Peking University
    2Beijing Advanced Innovation Center for Integrated Circuits, Peking University

Tuesday, April 23, 3:20 PM~4:40 PM Mezzanine A+B
T5 ： Ferroelectric Material & Memory

  • 3:20 PM~3:40 PM
    T5-1 The Impact of Thermal Noise in Multi-Domain Hf-based Antiferroelectric Material: Phase Transition and Endurance Performance
    Sheng Luo1, Zijie Zheng1, Zuopu Zhou1, Xiao Gong1, Gengchiau Liang1,2
    1Department of Electrical and Computer Engineering, National University of Singapore (NUS)
    2Industry Academia Innovation School, National Yang-Ming Chiao Tung University
  • 3:40 PM~4:00 PM
    T5-2 Ferroelectric Properties of HZO Orthorhombic (Pca21, Pmn21) Phases under Shear Strain -A Theoretical Study
    Yun-Wen Chen1 and C. W. Liu1,2,3
    1Graduate Institute of Electronics Engineering
    2Graduate Institute of Photonics and Optoelectronic
    3Graduate School of Advanced Technology, National Taiwan University
  • 4:00 PM~4:20 PM
    T5-3 BEOL-Compatible Ferroelectric Capacitor with Excellent Endurance and Retention by Improving Interface Quality
    Li-Cheng Teng1, Yu-Che Huang2, Shin-Yuan Wang1, Yu-Hsien Lin3 and Chao-Hsin Chien1
    1Institute of Electronics, National Yang Ming Chiao Tung University
    2International College of Semiconductor Technology, National Yang Ming Chiao Tung University
    3Department of Electronics Engineering, National United University
  • 4:20 PM~4:40 PM
    T5-4 Morphotropic Phase Boundary-Enhanced Polarization and High-Temperature Retention in Ferroeletric FET
    Y.-T. Tang, C.-S. Pai, Z.-R. Haung, Y.-T. Tsai, Z.-K. Chen, Dept of Electrical Engineering, National Central University

Wednesday, April 24, 10:20 AM~12:00 PM Ballroom A
T6 ： Embedded Memory and Sensor

  • 10:20 AM~10:40 AM
    T6-1 U-MRAM PUF: A Novel Unipolar-MRAM for Power and Area Efficient Hardware Root of Trust
    Ching Shih1,2, Ming-Chun Hong1,2, Chih-Yao Wang2, Guan-Long Chen2,Hsin-Han Lee2, Kuan-Ming Chen2, Bo-Chen Chiou2, Yao-Jen Chang2, Shan-Yi Yang2, Sin-You Huang2, Chiao-Yun Lo2, Yi-Hui Su, I-Jung Wang2, Chen-Yi Shih2, Shih-Ching Chiu2, Yu-Chen Hsin, Jeng-Hua Wei2, Shyh-Shyuan Sheu2,Wei-Chung Lo2, Shih-Chieh Chang2, Tuo-Hung Hou1,3
    1Institute of Electronics, National Yang Ming Chiao Tung University
    2Electronic and Optoelectronic System Research Laboratories, Industrial Technology Research Institute
    3Industrial Academia Innovation School, National Yang Ming Chiao Tung University
  • 10:40 AM~11:00 AM
    T6-2 A New Design of Ultra-scaled and High-density 1-nm Node 6T-SRAM Cell by Lateral-and-Complementary FETs (LC-FETs) with only 21 F2
    Kai-Wen Cheng, You-Jin Liu, E Ray Hsieh, National Central University
  • 11:00 AM~11:20 AM
    T6-3 A New Ultra-Low Voltage Metal Fuse for High Density OTP Applications
    Li-Yu Wang1, Kuan-Ju Chen1, Perng-Fei Yuh3, Yih Wang3, Jonathan Chang3, Ya-Chin King1, Chrong Jung Lin1,2
    1Institute of Electronics Engineering
    2College of Semiconductor Research, National Tsing Hua University (NTHU)
    3Taiwan Semiconductor Manufacturing Company (TSMC)
  • 11:20 AM~11:40 AM
    T6-4 Charge Trap Flash with Superior Program Efficiency by Negative Capacitance-boosting Effect
    Giuk Kim, Hyojun Choi, Sangho Lee, Hunbeom Shin, Lingwei Zhang, Sangmok Lee, Yunseok Nam, Woongjin Kim, Jihye Ock, Sujeong Lee, Hyunjun Kang, Sanghun Jeon, Korea Advanced Institute of Science and Technology
  • 11:40 AM~12:00 PM
    T6-5 Complementary Detectors for DUV Sensing by CMOS Logic Technology
    Ting-Kai Huang1, Hsin-Hung Yeh2, Jiaw-Ren Shih2, Chrong-Jung Lin2, Ya-Chin King2
    1College of Semiconductor Research, National Tsing Hua University
    2Institute of Electronics Engineering, National Tsing Hua University

Wednesday, April 24, 10:20 AM~11:40 AM Ballroom C
T8 ： Power Device/Circuit and Energy

  • 10:20 AM~10:40 AM
    T8-1 Investigations of Performances in RF GaN MIS-HEMTs and T-gate Schottky HEMTs with Leakage Current Analysis Using Emission Microscopy
    Chin-Ya Su1, Meng-Che Tsai2, Anant Johari1, 3, Ankur Gupta4, Rajendra Singh3, and Tian-Li Wu1,2,5
    1International College of Semiconductor Technology, National Yang Ming Chiao Tung University
    2Institute of Pioneer Semiconductor Innovation, National Yang Ming Chiao Tung University
    3Department of Physics, Indian Institute of Technology Delhi. 4Centre of Applied Research in Electronics, Indian Institute of Technology Delhi
    5Institute of Electronics, National Yang Ming Chiao Tung University
  • 10:40 AM~11:00 AM
    T8-2 Investigation of AlGaN/GaN MISHEMTs with Varied AlGaN Barrier Depths via a Low Damage ALE Process
    An-Chen Liu1, Hsin-Chu Chen2, Po-Tsung Tu1, 3,Sung-Jin Cho4, Andrew Newton4, Yung-Yu Lai5, Yan-Lin Chen6, Po-Chun Yeh3,Shu-Tong Chang6, and Hao-Chung Kuo1, 7, Fellow, IEEE
    1Department of Photonics and Institute of Electro-Optical Engineering, National Yang Ming Chiao Tung University,
    2Institute of Advanced Semiconductor Packaging and Testing, National Sun Yat-sen University
    3Electronic and Optoelectronic System Research Laboratories, Industrial Technology Research Institute
    4Oxford Instruments Plasma Technology
    5Research Center for Applied Sciences, Academia Sinica
    6Department of Electrical Engineering, National Chung Hsing University
    7Semiconductor Research Center, Hon Hai Research Institute
  • 11:00 AM~11:20 AM
    T8-3 Optimizing Al doped hafnium oxide in 3D trench capacitors for energy storage applications
    Alison E. Viegas1, Kati Kuehnel1, Konstantinos E. Falidas1, Matthias Rudolph1, Malte Czernohorsky1, Johannes Heitmann2
    1Fraunhofer IPMS – Center Nanoelectronic Technologies (CNT), Dresden, Germany
    2Institute of Applied Physics, Technische Universität Bergakademie Freiberg, Freiberg, Germany
  • 11:20 AM~11:40 AM
    T8-4 Investigation of Latch-up Immunity in 0.18-μm BCD Process with Deep Trench Isolation
    Wen-Yung Ho1, Ming-Dou Ker1, Chun-Chi Wang2, Tsung-Yin Chiang2, and I-Ju Wei2
    1Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan.
    2Elan Microelectronics Corp., Hsinchu, Taiwan.

Thursday, April 25, 10:20 AM~11:20 AM Ballroom A
T10 ： IGZO Devices

  • 10:20 AM~10:40 AM
    T10-1 Effects of Source/Drain Electrodes on Thermal Stability of IGZO FETs in the Oxygen-Deficient Environment
    Qiwen Kong, Long Liu, Kaizhen Han, Chen Sun, Leming Jiao, Zuopu Zhou,Zijie Zheng, Haiwen Xu, Jishen Zhang, Gan Liu, Xiao Gong, National University of Singapore (NUS)
  • 10:40 AM~11:00 AM
    T10-2 Transport Study of PEALD IGZO TFT at Cryogenic Temperatures down to 6 K
    Wenhui Wang1, Meishan Zhang1, Jun Lan1, Jiqing Lu1, Mei Shen1, Feichi Zhou1, Longyang Lin1, Panpan Zhang2, Yida Li1
    1School of Microelectronics, Southern University of Science and Technology
    2State Key Laboratory of Information Photonics and Optical Communications
  • 11:00 AM~11:20 AM
    T10-3 Amorphous IGZO-based 1T0C Charge-Trapping RAM with Excellent Retention
    Haisu Zhang1, Lin Bao2, Zongwei Wang1, Junchen Dong1, Dedong Han1, Shanguo Huang2,Yimao Cai1, Ru Huang1
    1Peking University
    2Beijing University of Posts and Telecommunications

Thursday, April 25, 11:25 AM~12:25 PM Ballroom A
T11 ： BEOL Technology

  • 11:25 AM~11:45 AM
    T11-1 Effect of Passivation on BEOL-Compatible Oxide Semiconductor Transistor
    Chi-Yuan Kuo1,3, Tsung-Tien Lo1, Yun-Ping Chiu1, Wei-Chen Lin2,3, Hsien-Yi Liao3, Chi-Hang Tsai3, Sheng-Chia Lu4, Hsin-Chu Chen5, Haw-Tyng Huang3, Po-Chun Yeh3, Yuh-Renn Wu1,3, Chih-I Wu1,3
    1National Taiwan University
    2National Tsing Hua University
    3Industrial Technology Research Institute
    4Scientific Gear Service
    5National Sun Yat-sen University
  • 11:45 AM~12:05 PM
    T11-2 Amorphous TeO2 as P-type Oxide Semiconductor for BEOL applications
    J Robertson1, X Zhang1, Q Gui2, Y Guo2
    1Engineering Dept, Cambridge University
    2Wuhan University
  • 12:05 PM~12:25 PM
    T11-3 Contact optimization through annealing and edge functionalization towards 2D TMD nanosheet devices
    Meng-Zhan Li1,2, Terry Y.T. Hung2, Wei Sheng Yun2, Sui An Chou2, Chen-Feng Hsu2, T.Y. Lee2, Chao-Ching Cheng2, Iuliana P. Radu2, and Minn-Tsong Lin1,3,4
    1Department of Physics, National Taiwan University
    2Corporate Research, Taiwan Semiconductor Manufacturing Company
    3Institute of Atomic and Molecular Sciences, Academia Sinica
    4Research Center for Applied Science, Academia Sinica

Tuesday, April 23, 1:40 PM~3:00 PM Ballroom C
D1 ： High-speed Circuits for Wireline Communication

Tuesday, April 23, 3:30 PM~4:30 PM Ballroom C
D2 ： Novel Accelerator Designs for Image Processing and AI

Wednesday, April 24, 10:20 AM~11:40 AM Mezzanine A+B
D4 ： New Paradigm for Physical Design Automation

  • 10:20 AM~10:40 AM
    D4-1 Standard Cell Structure and Transistor Reordering for Mitigating Area Penalty in Dual Diffusion Break FinFET Process
    Shinichi Nishizawa and Shinji Kimura,Waseda University
  • 10:40 AM~11:00 AM
    D4-2 On DRC Cleanness of Cell Porting for Design Migrations in Foundries and Technologies
    Ching-Ying Wang1,Chen-Ho Chen1,Po-Hsiang Chang2, Chien-Yu Hsieh2, Ching-Feng Su2, Scott Li2, Chien-Nan Liu1 and Hung-Ming Chen1
    1 National Yang Ming Chiao Tung University
    2 NovaTek Inc.
  • 11:00 AM~11:20 AM
    D4-3 Detailed Placement Refinement for Via Pillar Insertion and Pin Accessibility
    Yung-Yuan Lan and Ting-Chi Wang, National Tsing Hua University
  • 11:20 AM~11:40 AM
    D4-4 Set-Pair Routing Solver with Layer-by-layer Formulation on ILP
    Yasuhiro Takashima, The University of Kitakyushu

Wednesday, April 24, 1:40 PM~3:00 PM Ballroom C
D5 ： Advanced Analog Circuit Techniques

  • 1:40 PM~2:00 PM
    D5-1 A 16-Channel Neural Signal Recording IC Achieving a 4-to-90-Hz Tunable High-Pass Cutoff Frequency Based on a PVT-Insensitive Pseudo-Resistance Technique
    Ruoyu Chu1,2, Jiahe Li 1,2 and Hongming Lyu1,3
    1 ShanghaiTech University
    2 University of Chinese Academy of Sciences
    3 Shanghai Engineering Research Center of Energy Efficient and Custom AI IC
  • 2:00 PM~2:20 PM
    D5-2 A 101-dB SFDR 98.5-dB DR 20-kHz BW Continuous Time Incremental ΔΣ ADC with FIR DAC and Robust Reset Timing for Sensor Interfaces
    Cheng-En Wei, Cheng-Wei Wang, Chen-Hao Hung, Chi-Han Wang, Chuan-Tai Chou, Duan-Sin Hung, Guan-Wei Lu and Chia-Hung Chen, National Yang Ming Chiao Tung University
  • 2:20 PM~2:40 PM
    D5-3 A 4th-order CTDSM with PVT-insensitive Inverter-based OTAs
    Ming Wei Kung and Hsin Shu Chen, National Taiwan University
  • 2:40 PM~3:00 PM
    D5-4 A Resistor-Based High-Resolution Temperature-to-Digital Converter
    Rui-Song Lee, Chak-Hong Lam, Wei-Hao Chen, Chi-Feng Liu, Cheng-Yen Tsai, Ching-Ju Lu and Chia-Hung Chen, National Yang Ming Chiao Tung University

Wednesday, April 24, 1:40 PM~3:00 PM Ballroom D
D6 ： Verification & Test for Secure and Energy-Efficient Systems

  • 1:40 PM~2:00 PM
    D6-1 QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL
    Lennart M. Reimann1, Anshul Prashar1, Chiara Ghinami1, Rebecca Pelke1, Dominik Sisejkovic2, Farhad Merchant3 and Rainer Leupers1
    1 RWTH Aachen University
    2 Robert Bosch GmbH
    3 Newcastle University
  • 2:00 PM~2:20 PM
    D6-2 Pattern Generation for Efficient Acceptability Verification of Approximate Circuits
    Wei-Ji Chao1, Alexandra Kourfali2, Natalia Lylina2, Jun-Tsung Wu1, Jing-An Yang1, Chih-Hao Wang2, Tong-Yu Hsieh1 and Hans-Joachim Wunderlich2
    1 National Sun Yat-sen University
    2 University of Stuttgart

  • 2:20 PM~2:40 PM
    D6-3 Branch-Aware Self-Test Program Generation for Processor Cores
    Li-An Kuo and Jiun-Lang Huang, National Taiwan University
  • 2:40 PM~3:00 PM
    D6-4 Dynamic IR-drop Prediction of At-speed Two-vector Tests Using Machine Learning
    Yu-Tsung Wu1, Zhe-Jia Liang1, Chao-Ho Hsieh1, Yun-Feng Yang1, Yung-Jen Lee1, James Chien-Mo Li1, Norman Chang2, Ying-Shiun Li2 and Lang Lin2
    1 National Taiwan University
    2 Ansys, Inc.

Wednesday, April 24, 1:40 PM~3:00 PM Mezzanine A+B
D7 ： AI Accelerator

  • 1:40 PM~2:00 PM
    D7-1 A Latch-based Stochastic Number Generator for Stochastic Computing of Extended Naïve Bayesian Network
    Ruilin Zhang1,2, Yangjun Xiao3, Jiawei Liu4, Xingyu Wang2, Shufan Xu1, Kunyang Liu1,2, Shinichi Nishizawa2, Kiichi Niitsu1 and Hirofumi Shinohara2
    1 Kyoto University
    2 Waseda University
    3 Lenovo
    4 China Construction Bank
  • 2:00 PM~2:20 PM
    D7-2 On-the-Fly Twiddle Factor Generator Design for Efficient Memory Management of Negative Wrapped Convolution
    Cheng-Siang Jheng, Yan-Ting Wu and Ming-Der Shieh, National Cheng Kung University
  • 2:20 PM~2:40 PM
    D7-3 SDM-SNN: Sparse Distributed Memory using Constant-Weight Fibonacci Code for Spiking Neural Network
    Yu-Xuan Zhou1 and Chih-Wei Liu1,2
    1 National Yang Ming Chiao Tung University
    2 Industrial Technology Research Institute
  • 2:40 PM~3:00 PM
    D7-4 Design of an Efficient Deep Neural Network Accelerator Based on Block Posit Number Representation
    Shen-Fu Hsiao1, Sin-Chen Lin1, Guan-Lin Chen1, Shih-Hua Yang1, Yen-Che Yuan1 and Kun-Chi Chen2
    1 National Sun Yat-sen University
    2 National Yang Ming Chiao Tung University

Wednesday, April 24, 3:30 PM~4:30 PM Ballroom D
D9 ： Optimization and Enhancement for Neural Networks

  • 3:30 PM~3:50 PM
    D9-1 Enhancing Solver Robustness through Constraint Tightening for DNN Compilation
    Chia-Wei Chang and Jing-Jia Liou, National Tsing Hua University
  • 3:50 PM~4:10 PM
    D9-2 An Efficient Approach to Iterative Network Pruning
    Chuan-Shun Huang1, Wuqian Tang1, Yung-Chih Chen2, Yi-Ting Li1, Shih-Chieh Chang1 and Chun-Yao Wang1
    1 National Tsing Hua University
    2 National Taiwan University of Science and Technology
  • 4:10 PM~4:30 PM
    D9-3 Training Process of Memristor-Based Spiking Neural Networks For Non-linearity
    Tsu-Hsiang Chen, Chih-Chun Chang, Chih-Tsun Huang and Jing-Jia Liou, National Tsing Hua University

Wednesday, April 24, 3:30 PM~4:30 PM Mezzanine A+B
D10 ： Digital Circuit

  • 3:30 PM~3:50 PM
    D10-1 An SVM-based Atrial Fibrillation Detection Processor IC with a 95.8-% Sensitivity for Low-Power Event-Driven Cardiac Monitoring Applications
    Kanjun Zhou1,2, Xinyue Gu1,2 and Hongming Lyu1,3
    1 ShanghaiTech University
    2 University of Chinese Academy of Sciences
    3 Shanghai Engineering Research Center of Energy Efficient and Custom AI IC
  • 3:50 PM~4:10 PM
    D10-2 A 919GMACs/J Reconfigurable SIMD Array Processor for Baseband Signal Processing
    Yu-Cheng Lin1,Ren-Hao Chiou1,Yu-Cheng Lin1 and Chia-Hsiang Yang1, 2
    1 National Taiwan University
    2 Industrial Technology Research Institute
  • 4:10 PM~4:30 PM
    D10-3 Low-latency High-throughput Multi-precision Fused Floating-point Division and Square-root Unit Design
    Liangtao Dai1, Haocheng Zhu1, Binzhe Yuan1, Chao Yang1, Yuan Wang2 and Xin Lou1
    1 ShanghaiTech University
    2 UESTC

Thursday, April 25, 10:20 AM~11:20 AM Mezzanine A+B
D13 ： Emerging Technology and Applications

  • the photo of Speaker
    10:20 AM~10:40 AM
    D13-1 (Invited) THz Electronics for Sensing and Communication Applications
    Chun-Hsing Li, National Taiwan University
  • 10:40 AM~11:00 AM
    D13-2 A Readout Integrated Circuit of Graphene-Silicon Charge-Sampling Devices for Weak-Light Detection Applications
    Xiaochen Wang, Jiangming Lin, Hao Ning, Yongliang Xie, Feng Tian, Yuxin Zheng, Weiping Ren, Xiaoxue Cao, Muhammad Abid Anwar, Zongwen Li, Zhixiang Zhang, Shuang Song, Yuda Zhao, Srikrishna Chanakya Bodepudi, Hongbo Zhu, Bin Yu and Yang Xu, Zhejiang University
  • 11:00 AM~11:20 AM
    D13-3 Optimization of CFET Standard Cell Using Double-Cell-Height Structure
    Liang-Chi Huang, Ko-Cheng Lu, Wei-Cheng Kang, Bo-Hsun Juan, Pen-Yi Chu, Chih-Hsuan Lu and Tzu-Hsuan Chang, National Taiwan University

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