Tuesday, April 23, 3:20 PM~4:50 PM Ballroom A

T4 ： Novel Quantum Computing Devices and Materials

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  3:20 PM~3:50 PM

  T4-1 Semiconductor spin qubits from lab to fab: recent progress and perspectives
  

  Louis Hutin, CEA-Leti
  

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• 
  3:50 PM~4:20 PM

  T4-2 Trends and Prospects of Silicon Quantum Bit Research
  

  Tetsuo Kodera, Tokyo Institute of Technology
  

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• 
  4:20 PM~4:50 PM

  T4-3 Device Implications and Optimization for Cryo-CMOS
  

  Nick Chiang, Taiwan Semiconductor Manufacturing Company, Ltd.
  

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Wednesday, April 24, 10:20 AM~11:50 AM Ballroom B

T7 ： 3D Transistor Generation-Device Technology and Application

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  10:20 AM~10:50 AM

  T7-1 The historical development of non-planar devices
  

  Digh Hisamoto, Hitachi, Ltd.
  

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• 
  10:50 AM~11:20 AM

  T7-2 Process Technology Innovation for Performance Improvements in the Era of Horizontal Gate-All-Around (hGAA) Devices
  

  Nicolas Breil, Applied Materials
  

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• 
  11:20 AM~11:50 AM

  T7-3 10th Anniversary on the Discovery of Third Breakdown: Implications and Applications
  

  Steve S Chung, National Yang Ming Chiao Tung University
  

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Wednesday, April 24, 1:40 PM~5:30 PM Ballrom A

T9 ： Emerging Technologies for High-performance Computing

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  1:40 PM~2:10 PM

  T9-1 2D Semiconductors from Spin-on Molecular Chemistries for Direct Large-Scale Integration
  

  Zakaria Al Balushi, UC Berkeley
  

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• 
  2:10 PM~2:40 PM

  T9-2 Wafer-scale 3D Integration of 2D Materials
  

  Saptarshi Das, Penn State University
  

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• 
  2:40 PM~3:10 PM

  T9-3 Quantum Computing with Silicon Spins
  

  Dominik Zumbuhl, University of Basel
  

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• 
  3:30 PM~4:00 PM

  T9-4 Architectural Challenge for Cryogenic Superconductor Computing
  

  Koji Inoue, Kyushu University
  

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• 
  4:00 PM~4:30 PM

  T9-5 The need for new materials in silicon photonics to enhance data througput
  

  Dries Van Thourhout, Ghent University & imec
  

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• 
  4:30 PM~5:00 PM

  T9-6 Modeling GAA nanosheet devices accounting for quantum-mechanical effects down to cryo temperature
  

  Luca Larcher, Applied Materials
  

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• 
  5:00 PM~5:30 PM

  T9-7 Solving 3D-IC Multiphysics Challenges With A Novel ML-Assisted Co-Optimization Methodology
  

  Lang Lin, Ansys Inc.
  

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Thursday, April 25, 10:20 AM~11:50 AM Ballroom B

T12 ： Advanced Memory Technology

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  10:20 AM~10:50 AM

  T12-1 Unconventional Spin-Orbit Torques (SOT) in Sputtered Materials for High Density High Speed MRAM
  

  Shan X. Wang, Stanford University
  

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• 
  10:50 AM~11:20 AM

  T12-2 Chalcogenide selectors for low voltage and high density memory applications
  

  Elia Ambrosi, Taiwan Semiconductor Manufacturing Company, Ltd.
  

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• 
  11:20 AM~11:50 AM

  T12-3 Hafnia-based (Anti-)Ferroelectric Devices for Next-generation High-speed Dense Memory 
  

  Sou-Chi Chang, Intel Corporation
  

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Wednesday, April 24, 10:20 AM~11:50 AM Ballroom D

D3 ： Reliability

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  10:20 AM~10:50 AM

  D3-1 Measurement Evaluation of BTI-induced Degradation Using Ring Oscillators
  

  Ryo Kishida, Toyama Prefecture University
  

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• 
  10:50 AM~11:20 AM

  D3-2 Radiation-induced Soft Errors in Digital Circuits
  

  Jun Furuta, Kyoto Institute of Technology
  

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• 
  11:20 AM~11:50 AM

  D3-3 Using Commercial Foundry Technology to Design Reliable ASICs for Aerospace Applications
  

  Marcel van de Burgwal, imec
  

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Wednesday, April 24, 3:30 PM~5:00 PM Ballroom C

D8 ： High-Performance Computing for AI

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  3:30 PM~4:00 PM

  D8-1 Computational Network-on-Chip as Convolution Engine
  

  Zhonghai Lu, KTH Royal Institute of Technology
  

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• 
  4:00 PM~4:30 PM

  D8-2 Application-Architecture Mapping for Energy-efficiency and High-Performance in Network-on-Chip-based Manycore Architectures
  

  Md Farhadur Reza, Eastern Illinois University
  

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• 
  4:30 PM~5:00 PM

  D8-3 Exploiting HPC Techniques to Parallelise Simulation of 10B+ Transistor SoCs
  

  Jonathan Balkind, University of California, Santa Barbara
  

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Thursday, April 25, 10:20 AM~11:50 AM Ballroom C

D11 ： Edge Computing

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  10:20 AM~10:50 AM

  D11-1 Enhancing Efficiency of Communication Assistive Devices with AI Technology
  

  Ying-Hui Lai, National Yang Ming Chiao Tung University
  

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• 
  10:50 AM~11:20 AM

  D11-2 Heterogeneous Hardware Acceleration Methodology on SoC FPGA Using High Level Synthesis
  

  Chi-Chia Sun, National Taipei University
  

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• 
  11:20 AM~11:50 AM

  D11-3 A Low-power Convolutional Neural Network Implemented in 40-nm CMOS Technology for Bearing Fault Diagnosis
  

  Yu-Pei Liang, National Chung Cheng University
  

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PAGE CONTENTS

• -T4 :
   Novel Quantum Computing Devices and Materials
• -T7 :
   3D Transistor Generation-Device Technology and Application
• -T9 :
   Emerging Technologies for High-performance Computing
• -T12 :
   Advanced Memory Technology
• -D3 :
   Reliability
• -D8 :
   High-Performance Computing for AI
• -D11 :
   Edge Computing