History of the Best Paper Award

2022:

• A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement

Co-authors: Xingyu Wang, Ruilin Zhang, Yuxin Wang, Kunyang Liu, Xuanzhen Wang and Hirofumi Shinohara

Waseda University

• Distributed Sorting Architecture on Multiple FPGA

Co-authors: Yi-Da Hsin, Yen-Shi Kuo and Bo-Cheng Lai

National Yang Ming Chiao Tung University

2021:

• An Adaptive Loop Gain Tracking Digital PLL Using Spectrum-Balancing Technique

Co-authors: Guan-Yu Su, Zhi-Heng Kang and Shen-Iuan Liu

National Taiwan University

• Chip Performance Prediction Using Machine Learning Techniques

Co-authors: Min-Yan Su¹, Wei-Chen Lin¹, Yen-Ting Kuo¹, Chien-Mo Li¹, Eric Jia-Wei Fang² and Sung S.-Y. Hsueh²

¹ National Taiwan University

²MediaTek Inc.

• Storage-Aware Scheduling Algorithm for Reservoir Switching Minimization on Digital Microfluidic Biochips

Co-authors: Ling-Yen Song, Chih-Shen Yeh, Chien-Nan Liu and Juinn-Dar Huang

National Yang Ming Chiao Tung University

2020:

• A 500nW-50µW Indoor Photovoltaic Energy Harvester with Multi-mode MPPT

Co-authors: Ming-Chia Chang, Min-Hsuan Wu and Shen-Iuan Liu

National Taiwan University

• Low-Active-Energy and Low-Standby-Power Sub-threshold ROM for IoT Edge Sensing Systems

Co-authors: Jinn-Shyan Wang, Chien-Tung Liu and Chao-Hsiang Wang

National Chung Cheng University

2019:

• A Power-efficient, Bi-directional Readout Interface Circuit for Cyclic-voltammetry Electrochemical Sensors

Co-authors: Yi-Chia Chen, Shao-Yung Lu, Jui-Hsiang Tsai and Yu-Te Liao

National Chiao Tung University

• Primitive Concept Identification In A Given Set of Wafer Maps

Co-authors: Ahmed Wahba¹, Chuanhe Shan¹, Li-C. Wang¹ and Nik Sumikawa²

¹ UCSB

² NXP

2018:

• A 1.86mJ/Gb/Query Bit-Plane Payload Machine Learning Processor in 90nm CMOS

Co-authors: Fang-Ju Ku, Tung-Yu Wu, Yen-Chin Liao, Hsie-Chia Chang, Wing Hung Wong and Chen-Yi Lee

National Chiao Tung University

• Using Range-equivalent Circuits for Facilitating Bounded Sequential Equivalence Checking

Co-authors: Yung-Chih Chen, Wei-An Ji, Chih-Chung Wang, Ching-Yi Huang, Chia-Cheng Wu, Chia-Chun Lin and Chun-Yao Wang

National Tsing Hua University

2017:

• Low-Latency Voltage-Racing Winner-Take-All (VR-WTA) Circuit for Acceleration of Learning Engine

Co-authors: Chai-Heng Wu, Ting-Sheng Chen, Ding-Yuan Lee, Tsung-Te Liu and An-Yeu (Andy) Wu

National Taiwan University

• Robust Test Pattern Generation for Hold-time Faults in Nanometer Technologies

Co-authors: Yu-Hao Ho, Yo-Wei Chen, Chih-Ming Chang, Kai-Chieh Yang and Chien-Mo Li

National Taiwan University

2016:

• A 7 GB/S Half-Rate Clock and Data Recovery Circuit with Compact Control Loop

Co-authors: Yu-Po Cheng, Yen-Long Lee, Ming-Hung Chien and Soon-Jyh Chang

National Cheng Kung University

• Overlay-aware Layout Legalization for Self-Aligned Double Patterning Lithography

Co-authors: Chong-Meng Huang and Shao-Yun Fang

National Taiwan University of Science and Technology

2015:

• A 127 fJ/conv. Continuous-Time Delta-Sigma Modulator with a DWA-Embedded Two-Step Time-Domain Quantizer

Co-authors: Chan-Hsiang Weng, Tzu-An Wei and Tsung-Hsien Lin

National Taiwan University

• Clock-Domain-Aware Test for Improving Pattern Compression

Co-authors: Kun-Han Tsai and Janusz Rajski

Mentor Graphics

2014:

• A 3.5-4GHz FMCW Radar Transceiver Design with Phase-Domain Oversampled Ranging by Utilizing a 1-bit Delta-Sigma TDC

Co-authors: Wei Zhang, Yizhi Han, Fei Chen,Bo Zhou, Xican Chen, Woogeun Rhee and Zhihua Wang

Tsinghua University

• Thermal-aware Dynamic Buffer Allocation for Proactive routing Algorithm on 3D Network-on-Chip Systems

Co-authors: Yuan-Sheng Lee, Hsien-Kai Hsin, Kun-Chih Chen, En-Jui Chang and An-Yeu Wu

National Taiwan University

2013:

• Worst-Case IR-Drop Monitoring with 1GHz Sampling Rate

Co-authors: Chen-Hsiang Hsu, Shi-Yu Huang, Ding-Ming Kwai and Yung-Fa Chou

National Tsing Hua University

2012:

• IMITATOR: A Deterministic Multicore Replay System with Refining Techniques

Co-authors: Shing-Yu Chen, Chi-Neng Wen, Geng-Hau Yang, Wen-Ben Jone and Tien-Fu Chen

National Chiao Tung University

• A Monolithic 1.85GHz 2-stage SiGe Power Amplifier with Envelope Tracking for Improved Linear Power and Efficiency

Co-authors: Ruili Wu, Yan Li, Jerry Lopez and Donald Y. C. Lie

Texas Tech. University

2011:

• Important Test Selection For Screening Potential Customer Returns

Co-authors: Nik Sumikawa, Dragoljub Gagi Drmanac, LeRoy Winemberg, Li-C. Wang, and Magdy S. Abadir

University of California, Santa Barbara

• A Macro-Layer Level Fully Parallel Layered LDPC Decoder SOC for IEEE 802.15.3c Application

Co-authors: Zhixiang Chen, Xiao Peng, Xiongxin Zhao, Qian Xie, Reona Okmura, Dajiang Zhou and Satoshi GoTo

Waseda University

2010:

• Traffic-Thermal Mutual-Coupling Co-Simulation Platform for Three-Dimensional Network-on-Chip

Co-authors: Kai-Yuan Jheng, Chih-Hao Chao, Hao-Yu Wang and An-Yeu Wu

National Taiwan University

2009:

• A 6-GS/s, 6-bit, at-speed testable ADC and DAC pair in 0.13µm CMOS

Co-authors: Chen-Kang Ho and Hao-Chiao Hong

National Chiao Tung University