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Tuesday, April 18, 3:40 PM~5:25 PM Ballroom A
T4 ： High Power Devices

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    3:40 PM~4:15 PM
    T4-1 Singapore’s First 200mm SiC Open Ecosystem Platform: Addressing Economics, Performances & Reliability of High-Power Devices, and Evolution into RF/mmWave Solutions
    Chand Umesh, A*STAR/IME Singapore
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    4:15 PM~4:50 PM
    T4-2 Advanced Substrates for Power Electronics
    Thierry Boudet, Soitec
  • 4:50 PM~5:25 PM
    T4-3 Comprehensive GaN-on-Si Power Device Platform with High Manufacturing Capacity and Quality
    David Zhou, Innoscience

Wednesday, April 19, 10:20 AM~12:05 PM Ballroom B
T6 ： Advanced Packaging Technologies

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    10:20 AM~10:55 AM
    T6-1 Moore’s Law in the Era of Polylithic Integration
    Muhannad S. Bakir, Georgia Institute of Technology
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    10:55 AM~11:30 AM
    T6-2 Advanced Packaging and Heterogenous Integration
    Subramanian (Subu) Iyer, University of California, Los Angeles
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    11:30 AM~12:05 PM
    T6-3 Opportunities and Challenges of 2.5D Packaging in the AI Data Center Era
    Shang Y. Hou, TSMC

Wednesday, April 19, 10:20 AM~12:05 PM Ballroom D
D3 ： Compute-in-Memory: From Architecture to Devices

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    10:20 AM~10:55 AM
    D3-1 Computing-in-Memory with Ferroelectric Materials and Beyond
    Darsen D. Lu, National Cheng Kung University
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    10:55 AM~11:30 AM
    D3-2 Digital-Assisted Analog In-Memory Computing with RRAM Devices
    Yu Cao, Arizona State University
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    11:30 AM~12:05 PM
    D3-3 Processing-in-memory (PIM)-based Manycore Architecture for Training Graph Neural Networks
    Partha P. Pande, Washington State University

Wednesday, April 19, 1:40 PM~5:30 PM Ballroom A
T8 ： Novel Channel Logic and 3D-stacked Transistors

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    1:40 PM~2:10 PM
    T8-1 Graphene and MoS2: Pushing the Limits of Electronics Through Heterogeneous Integration
    Tomás Palacios, Massachusetts Institute of Technology
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    2:10 PM~2:40 PM
    T8-2 Epitaxial Growth of Transition Metal Dichalcogenide Monolayers and Heterostructures for Large Area Device Applications
    Joan Redwing, Pennsylvania State University
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    2:40 PM~3:10 PM
    T8-3 Contacts and Dielectrics for Two-Dimensional Semiconductors
    William Vandenberghe, The University of Texas at Dallas
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    3:30 PM~4:00 PM
    T8-4 Hybrid 2D/CMOS Microchips for Memristive Technologies
    Mario Lanza, King Abdullah University of Science and Technology
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    4:00 PM~4:30 PM
    T8-5 Overview of scalable transfer approaches to enable epitaxial 2D material integration
    Steven Brems, imec
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    4:30 PM~5:00 PM
    T8-6 Selective Dielectric on Dielectric (DOD) achieved on SiO2 in Preference to W by 300°C Aniline Passivation and Water-free Chemical Vapor Deposition
    Andrew Kummel, University of California, San Diego
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    5:00 PM~5:30 PM
    T8-7 Contact Resistance of n- and p-type 2D Semiconductors MoS2 and WSe2 with Moire Interfaces
    John Robertson, University of Cambridge

Wednesday, April 19, 3:30 PM~5:15 PM Ballroom C
D6 ： Security and Encryption

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    3:30 PM~4:05 PM
    D6-1 A Survey on Hardware Security Techniques for Preventing Reverse Engineering Attacks
    Shih-Hsu Huang, Chung Yuan Christian University
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    4:05 PM~4:40 PM
    D6-2 The Next Big Thing: IoT Applications with Data Privacy-enhancing Technologies
    Yao-Tung Tsou, DeCloak Intelligences Co.
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    4:40 PM~5:15 PM
    D6-3 A Next-Generation Side-Channel Detector for General-Purpose Processors
    Trevor E. Carlson, National University of Singapore

Thursday, April 20, 10:20 AM~12:05 PM Ballroom C
D8 ： Advanced Process-induced Design Challenges and Solutions

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    10:20 AM~10:55 AM
    D8-1 AI Computing in Large-Scale Era : Pre-trillion-scale Neural Network Models and Exa-scale Supercomputing
    Bor-Sung Liang, MediaTek Inc.
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    10:55 AM~11:15 AM
    D8-2 Accurate and Efficient Aging-aware Static Timing Analysis
    James Ng, Synopsys
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    11:15 AM~11:25 AM
    D8-3 Activity-Based Aging Assessment
    Kevin Chen, TSMC
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    11:30 AM~12:05 PM
    D8-4 On Generating Cell Library in Advanced Nodes: Efforts and Challenges
    Hung-Ming Chen, National Yang Ming Chiao Tung University

Thursday, April 20, 10:20 AM~12:40 PM Ballroom B
T10 ： Dielectric Stacking and Interface Engineering

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    10:20 AM~10:55 AM
    T10-1 Interface tailoring for CMOS, cryogenic electronics, and beyond
    Minghwei Hong, National Taiwan University
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    10:55 AM~11:30 AM
    T10-2 Nanosheet Extensions and Beyond
    Chee Wee Liu, National Taiwan University
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    11:30 AM~12:05 PM
    T10-3 High Vth Ferroelectric Gate Stack GaN HEMT for Power Switching Applications
    Edward Yi Chang, National Yang Ming Chiao Tung University
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    12:05 PM~12:40 PM
    T10-4 Ferroelectric Engineering of FeFET Toward Multi-Level Coding for High-Density Nonvolatile Memory
    Min-Hung Lee, National Taiwan Normal University

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