Tuesday, April 18, 12:50 PM~5:00 PM Ballroom D
T1 Poster Session

  • T1-1 Characterization of 4H-SiC PMOSFET with P+ Poly-Si Gate
    Chia-Lung Hung1, 2 and Bing-Yue Tsui1
    1National Yang Ming Chiao Tung University
    2Hon Hai Research Institute
  • T1-2 Effects of Deep Trench Isolation Shape and Microlens Radius of Curvature on Optical and Electrical crosstalk in Backside Illuminated CMOS Image Sensors
    Eknath Sarkar, Yichen Ma, Yu-Chieh Lee and C. W. Liu
    National Taiwan University
  • T1-3 The Impact of Nano CMOS Device Scaling on High Frequency Performance and Optimization Principle for fMAX Boost
    Adhi Cahyo Wijaya, Jinq-Min Lin and Jyh-Chyurn Guo
    National Yang Ming Chiao Tung University
  • T1-4 Characterization and Current Modeling of Stacked high-k Metal-Insulator-Metal Capacitors
    Gui-Sheng Chao, Wei-Hua Chen, Kuan-Ju Chen, Chrong-Jung Lin and Ya-Chin King
    National Tsing Hua University
  • T1-5 Low-temperature & high yield transfer approaches for embedding the 4th generation semiconductor Ga2O3 on the high thermal conductive substrate
    Bi-Xian Wu, Rong-Turng Lin and Tzu-Hsuan Chang
    National Taiwan University
  • T1-6 Simulation and Investigation of Gate-Stack Variations in Ferroelectric-FET (FeFET) with Double-Gate Structure
    Lung-En Chang and Pin Su
    National Yang Ming Chiao Tung University
  • T1-7 A Kinetic Monte Carlo Simulation Study of WS2 RRAM with Different 2D Layer Thickness
    Ying-Chuan Chen1,2, Yu-Ting Chao1, Edward Chen2, Chao-Hsin Wuand Yuh-Renn Wu1
    1National Taiwan University
    2Taiwan Semiconductor Manufacturing Co., Ltd.
  • T1-8 A High-energy-difference Design for Boltzmann Machine-based Invertible Logic
    Yihan He, Chao Fang, Sheng Luo and Gengchiau Liang
    National University of Singapore
  • T1-9 Investigation of Hydrogen Diffusion in Top Gate IGZO TFTs by Using Various Pulse-Width Operation Method and Capacitance-Voltage Analysis
    Yu-An Chen, Ting-Chang Chang, Ya-Ting Chien, Po-Yi Lee and Kui-You Shao
    National Sun Yat-sen University
  • T1-10 Saturation of Transient Current Read at Millisecond-Scale in MOS Capacitor with Ultra-Thin Oxide when Switching
    Sung-Wei Huang and Jenn-Gwo Hwu
    National Taiwan University
  • T1-11 Study of SiC trench MOSFET switching performance
    Chih-Hung Yen1, Yu-Ting Chen1, Hua-Mao Chen1, Shin-Yi Huang1, Mei-Ju Lee1, Chih-Ming Lai1, Li-Tien Hsuehand Jui-Cheng Wang2
    1Industrial Technology Research Institute
    2National Yang Ming Chiao Tung University
  • T1-12 Architecture Dependent Constraint-Aware RFET Based 1T-DRAM
    Sandeep Semwal, Rohit Kumar Nirala, Nivedita Rai and Abhinav Kranti
    Indian Institute of Technology Indore
  • T1-13 Warpage Assessment of System in Wafer-level Package Technology with RDL Process through Theoretical Approach and Experimental Validation
    Ching-Feng Yu, Chao-Kai Hsu and Chih-Cheng Hsiao
    Industrial Technology Research Institute
  • T1-14 Ultra High-k HfZrO4 Thin Films Grown by Atomic Layer Deposition using Metal-Organic and Brute HOOH precursors
    Harshil Kashyap1, Marshall Benham2, Jeffrey Spiegelman2 and Andrew Kummel1
    1University of California San Diego
  • T1-15 Enhanced Device Characteristics of InGaAs MOSFETs Using High Switching Speed Ferroelectric Material
    Ping Huang, Mu-Yu Chen and Edward-Yi Chang
    National Yang Ming Chiao Tung University
  • T1-16 Effect of O2 plasma surface treatment on gate leakage current in AlGaN/GaN HEMT
    An-Chen Liu1, Yu-Wen Huang1, Chao-Hsu Lin1, Yi-Jun Dong1, Yung-Yu Lai3, Chao-Cheng Ting1, Po-Tsung Tu2, Po-Chun Yeh2, Hsin-Chu Chenand Hao-Chung Kuo1
    1National Yang Ming Chiao Tung University
    2Industrial Technology Research Institute
    3Academia Sinica
  • T1-17 Voltage- and Current-mode ÷3 Injection-Locked Frequency Divider
    Ho-Chang Lee, Sheng-Lyang Jang and Dan-Li Wang
    National Taiwan University of Science and Technology
  • T1-18 Thomas-Fermi interfacial screening with voltage-dependence of the screening lengths and influence of oxygen vacancies in MFTJs
    Deepali Jagga and Artur Useinov
    National Yang Ming Chiao Tung University
  • T1-19 Improving the fabricated Rate and Reliability of Top Gate a-IGZO TFTs under Positive Bias Stress by Using Double-Stacked Gate Insulator Layer Design
    Bo-Shen Huang, Ting-Chang Chang, Mao-Chou Tai and Po-Yu Yen
    National Sun Yat-sen University
  • T1-20 Integrated High Aspect Ratio 3D High Density Capacitor in Si Interposer for 2.5D Advanced Packaging Applications
    Chun-Lin Lu, Cheng-Shu Ho, Kuo-Wei Liu, Guan-Deng Wang, Min-Syong Ju, Ka Man So,
    Kai-Yao Shih, Miller Liao and Shou-Zen Chang
    Powerchip Semiconductor Manufacturing Corporation

Tuesday, April 18, 1:40 PM~3:20 PM Ballroom A
T2 GaN HEMT Physics and Design

  • 1:40 PM~2:00 PM
    T2-1 GaN on Si RF performance with different AlGaN back barrier
    Chang-Yan Hsieh1, Hui-Yu Chen1, Po-Tsung Tu1,2, Jui-Chin Chen1, Hsin-Yun Yang1, Po-Chun Yeh1, De Hsieh1, Hsueh-Hsing Liu1, Yi-Keng Fu1, Shyh-Shyuan Sheu1, Hao-Chung Kuo2, Yuh-Renn Wu1, Wei-Chung Lo1 and Shih-Chieh Chang1
    1Industrial Technology Research Institute
    2National Yang Ming Chiao Tung University
  • 2:00 PM~2:20 PM
    T2-2 DC/RF Performance and Reliability of 100-nm Gate Length AlGaN/GaN MIS-HEMTs with Different Thickness of in-situ SiN
    Chin-Ya Su, Meng-Che Tsai and Tian-Li Wu
    National Yang Ming Chiao Tung University
  • 2:20 PM~2:40 PM
    T2-3 Investigation on ESD Robustness of 1200-V D-Mode GaN MIS-HEMTs with HBM ESD Test and TLP Measurement
    Chao-Yang Ke, Wei-Cheng Wang, Ming-Dou Ker, Chih-Yi Yang and Edward Yi Chang
    National Yang Ming Chiao Tung University
  • 2:40 PM~3:00 PM
    T2-4 Performance Improvement of GaN HEMT with Ferroelectric Gate Stacks for RF/mm-Wave Switching Applications
    Yu-En Jeng, Hansheng Ye, Govind Bajpai and Patrick Fay
    University of Notre Dame
  • 3:00 PM~3:20 PM
    T2-5 Investigating the Relationship Between Kink Voltage and Width Effect in GaN-on-SiC HEMTs
    Yi-Zhen Wu1, Fu-Yuan Jin1, Ting-Tzu Kuo1, Po-Hsun Chen2 and Ting-Chang Chang1
    1National Sun Yat-sen University
    2R. O. C. Naval Academy

Tuesday, April 18, 1:40 PM~3:20 PM Ballroom C
D1 Clocking Circuits

  • 1:40 PM~2:00 PM
    D1-1 A 7~10.5-Gb/s Reference-Less Linear Half-rate CDR Circuit Using Automatic Band Selector
    Yi-En Hsu and Shen-Iuan Liu, National Taiwan University
  • 2:00 PM~2:20 PM
    D1-2 A Sub-Sampling Phase-Locked Loop with a TDC-Based Frequency-Locked Loop
    Yu-Meng Hong and Tsung-Hsien Lin, National Taiwan University
  • 2:20 PM~2:40 PM
    D1-3 A Sub-Sampling Phase-Locked Loop With a Robust Agile-Locking Frequency-Locked Loop
    Chia-Min Chen, Yu-Meng Hong and Tsung-Hsien Lin, National Taiwan University
  • 2:40 PM~3:00 PM
    D1-4 A 0.02mm2 Sub-Sampling PLL with Spur Reduction Technique in 90nm CMOS Technology
    Sheng-Jen Cheng1, You-Rong Qiu1, Chia Hsuan Li2, Chung-Hung Hong3, Chung-Ping Chen1 and Wei-Yi Liu1
    1National Taiwan University
    2Fu Jen Catholic University
    3Chang Gung Memorial Hospital
  • 3:00 PM~3:20 PM
    D1-5 High Swing VCO with Current-Reused Frequency Doubler and Darlington Amplifier
    Sheng-Jen Cheng1, Sheng–Lyang Jang2, Hui Chen2, Chung-Hung Hong3 and Chung-Ping Chen1
    1National Taiwan University
    2National Taiwan University of Science and Technology
    3Chang Gung Memorial Hospital

Tuesday, April 18, 1:40 PM~3:40 PM Mezzanine A+B
T3 Advanced Transistor Technology

  • 1:40 PM~2:00 PM
    T3-1 Effect of Ga-Doping on Atomic-Layer-Deposited Ultrathin InGaO Thin Film Transistors with BEOL-Compatibility
    Jie Zhang, Zhuocheng Zhang, Dongqi Zheng, Zehao Lin, Adam Charnas and Peide. D. Ye
    Purdue University
  • 2:00 PM~2:20 PM
    T3-2 Stacked Two Ge0.98Si0.02 Nanowire nFETs with High-κ Dielectrics Featuring High ION per Footprint of 4800 μA/μm at VOV=VDS=0.5V
    Yu-Rui Chen, Chien-Te Tu, Zefu Zhao, Yi-Chun Liu, Bo-Wei Huang, Yifan Xing, Guan-Hua Chen and C. W. Liu
    National Taiwan University
  • 2:20 PM~2:40 PM
    T3-3 Vertical GeSn/SiGeSn GAA Nanowire n-FETs with High Electron Mobility
    Yannik Junk1, Marvin Frauenrath2, Yi Han1, Jingxuan Sun1, Omar Concepción Diaz1, Jin-Hee Bae1, Jean-Michel Hartmann2, Detlev Grützmacher1, Dan Buca1 and Qing-Tai Zhao1
    1Forschungszentrum Jülich
    2University of Grenoble Alps
  • 2:40 PM~3:00 PM
    T3-4 Low Dit of (2-4) x 1010 eV-1cm-2 using Y2O3/epi-Si/Ge Gate Stacks
    Hsien-Wen Wan1, Yi-Ting Cheng1, Chao-Kai Cheng1, Tien-Yu Chu1, Tun-Wen Pi2, Jueinai Kwo3 and Minghwei Hong1
    1National Taiwan University
    2National Synchrotron Radiation Research Center
    3National Tsing Hua University
  • 3:00 PM~3:20 PM
    T3-5 BEOL Design and RF Performance of Stacked Si Nanosheets and Nanowires
    Hsin-Cheng Lin, Kung-Ying Chiu, Ching-Wang Yao, Tao Chou, Tsai-Yu Chung and C. W. Liu
    National Taiwan University
  • 3:20 PM~3:40 PM
    T3-6 Attainment of nearly thermally limited subthreshold slope in GaAs MOSFETs with in-situ Y2O3 gate dielectric for cryogenic electronics
    L.B. Young1, J. Liu1, Y.-H. G. Lin1, H.-W. Wan1, Y.-T. Cheng1, J. Kwo2 and M. Hong1
    1National Taiwan University
    2National Tsing Hua University

Tuesday, April 18, 3:50 PM~5:30 PM Ballroom C
D2 Analog and Mixed Signal Techniques

  • 3:50 PM~4:10 PM
    D2-1 A 0.0072-mm2 10-bit 100-MS/s Calibration-free SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOS
    Yao-Hung Tsai and Shen-Iuan Liu, National Taiwan University
  • 4:10 PM~4:30 PM
    D2-2 A 411nA Quiescent Current Hysteretic Buck Converter with Self-Control Biasing and Dynamic Voltage Scaling (DVS) for IoT Applications
    Wei-Ting Yeh, Guan-Shen Yao, Chun-Yu Chen and Chien-Hung Tsai, National Cheng Kung University
  • 4:30 PM~4:50 PM
    D2-3 A CMOS Buffer Amplifier with Slew-Rate Enhancement and Power Saving Techniques
    Liang-Jie Lu, Po-Hsun Chu, Wei-Chen Huang and Yu-Te Liao, National Yang Ming Chiao Tung University
  • 4:50 PM~5:10 PM
    D2-4 A Low Power Readout Circuit for a Tri-axial Piezoelectric MEMS Accelerometer
    Sin-Yu Ciou and Soon-Jyh Chang, National Cheng Kung University
  • 5:10 PM~5:30 PM
    D2-5 A 200 nA Quiescent Current N-FinFET Power Stage Buck Converter with Passive Ramp On-Off-Time Control in 12 nm FinFET
    Ching-Yang Wu1, Chieh-Ju Tsai1, Ching-Jan Chen1, Chien-Cheng Tu2, Szu-Ting Wang2 and Yong-Hwa Wen2
    1National Taiwan University

Wednesday, April 19, 10:20 AM~12:20 PM Ballroom A
T5 Ferro RRAM

  • 10:20 AM~10:40 AM
    T5-1 Demonstration of Large Polarization in Si-doped HfO2 Metal–Ferroelectric–Insulator–Semiconductor Capacitors with Good Endurance and Retention
    Jing-Hua Hsuen1, Maximillian Lederer2, Lars Kerkhofs3,4, Yannick Raffel2, Luca Pirro5, Talha Chohan5, Konrad Seidel2, Thomas Kämpfe2, Sourav De2 and Tian-Li Wu1,4
    1National Yang Ming Chiao Tung University
    2 Fraunhofer IPMS - Center Nanoelectronic Technologies
    3Faculty of Engineering Science, KU Leuven
    4National Yang Ming Chiao Tung University
  • 10:40 AM~11:00 AM
    T5-2 NLS based Modeling of Temperature-dependent Phase Transition Characteristics for Antiferroelectric/Ferroelectric Hafnium Zirconium Oxides
    Yu-Chen Chen1, Kuo-Yu Hsiang1,2, Min-Hung Lee2 and Pin Su1
    1National Yang Ming Chiao Tung University
    2National Taiwan Normal University
  • 11:00 AM~11:20 AM
    T5-3 Demonstration of Differential Mode FeFET-Array for multi-precision storage and IMC applications
    Vivek Parmar1, Franz Müller2, Jing-Hua Hsuen3, Sandeep Kaur Kingra1, Yannick Raffel2, Maximillian Lederer2, Tarek Ali4, Stefan Dünkel4, Konrad Seidel2, Sven Beyer4, Tian-Li Wu3, Thomas Kämpfe2, Sourav De2 and Manan Suri1
    1Indian Institute of Technology Delhi
    2Fraunhofer IPMS – Center Nanoelectronic Technologies
    3National Yang Ming Chiao Tung University
  • 11:20 AM~11:40 AM
    T5-4 ZrAlxOy high-k dielectrics for MIM decoupling capacitors in the BEOL
    Konstantinos Falidas1, Konstantin Mertens1, Maximilian Everding1, Malte Czernohorsky1 and Johannes Heitmann2
    1Fraunhofer IPMS – Center Nanoelectronic Technologies
    2Technische Universität Bergakademie Freiberg
  • 11:40 AM~12:00 PM
    T5-5 Fabrication of Low-Power RRAM for Stateful Hyperdimensional Computing
    T. Dubreuil, S. Barraud, B. Previtali, S. Martinie, J. Lacord, S. Martin, N. Castellani, A. Anotta and F. Andrieu
  • 12:00 PM~12:20 PM
    T5-6 28nm HKMG 1F-1R2 Multilevel Memory for Inference Engine Application
    Sourav De1, Franz Müller1, Maximilian Lederer1, Yannick Raffel1, Tarek Ali2, Luca Pirro2, Stefan Dünkel2, Sven Beyer2, Konrad Seidel1 and Thomas Kämpfe1
    1Fraunhofer IPMS – Center Nanoelectronic Technologies

Wednesday, April 19, 10:20 AM~12:00 PM Ballroom C
T7 New Application Opportunities on Silicon Technology

  • 10:20 AM~10:40 AM
    T7-1 16nm FinFET DUV Detector Array in Fully Compatible FinFET Logic Process
    Wei-Hwa Lin1, Jiaw-Ren Shih1, Jonathan Chang2, Yih Wang2, Perng-Fei Yuh2, Ya-Chin King1 and Chrong Jung Lin1
    1National Tsing Hua University
    2Taiwan Semiconductor Manufacturing Company
  • 10:40 AM~11:00 AM
    T7-2 Offset-Via Anti-fuse by Cu BEOL Process in Advanced CMOS Technologies
    Li-Yu Yeh, Chrong-Jung Lin and Ya-Chin King
    National Tsing Hua University
  • 11:00 AM~11:20 AM
    T7-3 Neuronal Function and Signal Amplification Device with Steep Switching “PN-Body Tied SOI-FET”
    Takayuki Mori and Jiro Ida
    Kanazawa Institute of Technology
  • 11:20 AM~11:40 AM
    T7-4 A High Sensitivity and Modulation Contrast Photonic Demodulator for Time-of-Flight Application
    Shun-Qi Dai1,2, Cristine Jin Estrada1,2, Annan Xiong1,2, Songcen Xu1,2, Huanmei Yuan1,2, Chen Xu3, Jie George Yuan1,2 and Mansun Chan1,2
    1The Hong Kong University of Science and Technology
    2 AI Chip Center for Emerging Smart Systems (ACCESS)
    3SmartSens Technology
  • 11:40 AM~12:00 PM
    T7-5 Demonstration of A 3D Chip by Logic-DRAM Stacked Using Paired TSV Interconnection through Interface for AI/Edge-Computing Application
    Chun-Lin Lu, Chun Cheng Chen, Sheng-Chieh Lin, Chih-Hao Chuang, Kai-Yao Shih, Hsin-Yi Liao, Chin-Hung Huang, Min-Syong Ju, Cheng-Shu Ho, Chi Ming Chen and Shou-Zen Chang
    Powerchip Semiconductor Manufacturing Corporation

Wednesday, April 19, 1:40 PM~3:00 PM Ballroom C
D4 AI and Security Chips

  • 1:40 PM~2:00 PM
    D4-1 A Novel Unified Modular Arithmetic Unit for Elliptic Curve Cryptography
    Hsiang-Yu Chen, Kuan-Ying Peng and Kuen-Jong Lee, National Cheng Kung University
  • 2:00 PM~2:20 PM
    D4-2 A Binary Weight Convolutional Neural Network Hardware Accelerator for Analysis Faults of the CNC Machinery on FPGA
    Ching-Che Chung, Yu-Pei Liang, Ya-Ching Chang and Chen-Ming Chang, National Chung Cheng University
  • 2:20 PM~2:40 PM
    D4-3 Minimizing Computation in Binarized Neural Network Inference using Partial-Filter Sharing
    You-Hsuen Tsai1, Yu-Chang Huang1, Yi-Ting Li1, Yung-Chih Chen2 and Chun-Yao Wang1
    1National Tsing Hua University
    2National Taiwan University of Science and Technology
  • 2:40 PM~3:00 PM
    D4-4 Accelerating Binarized Neural Network Inference by Reusing Operation Results and Elevating Resource Utilization on Edge Devices
    Yu-Chang Huang1, You-Hsuen Tsai1, Yi-Ting Li1, Yung-Chih Chen2 and Chun-Yao Wang1
    1National Tsing Hua University
    2National Taiwan University of Science and Technology

Wednesday, April 19, 1:40 PM~3:00 PM Ballroom D
D5 Optimized Hardware Implementation for Domain-Specific Accelerators

  • 1:40 PM~2:00 PM
    D5-1 Hardware-aware Model Architecture for Ternary Spiking Neural Networks
    Nai-Chun Wu, Tsu-Hsiang Chen and Chih-Tsun Huang, National Tsing Hua University
  • 2:00 PM~2:20 PM
    D5-2 Accelerating LU-decomposition of Arbitrarily Sized Matrices on FPGAs
    Maram Krishna Kumar, Ziaul Choudry and Suresh Purini, International Institute of information Technology (IIIT), Hyderabad
  • 2:20 PM~2:40 PM
    D5-3 Area Efficient VLSI ASIC Implementation of Multilayer Perceptrons
    Rajeev Joshi, Lakshmi Kavya Kalyanam and Srinivas Katkoori, University of South Florida
  • 2:40 PM~3:00 PM
    D5-4 Design of Lower-Error and Area-Efficient Sine Function Generators for Image Encryptions Using Logarithmic Number Systems (LNS)
    Tso-Bing Juang, Wei-Cheng Lin, Guan-Zhong Lin and Shi-Jie Jian, National Pingtung University

Wednesday, April 19, 3:30 PM~5:10 PM Ballroom D
D7 New Ideas in Design Automation and Test

  • 3:30 PM~3:50 PM
    D7-1 A Built-In Self-Calibration Scheme for Memristor-Based Spiking Neural Networks
    Chi Tung, Kuan-Wei Hou and Cheng-Wen Wu, National Tsing Hua University
  • 3:50 PM~4:10 PM
    D7-2 Machine Learning based Routing Guide Generation and its Application to Design Rule Violation Reduction
    Chen-Han Lu1, Hsin-Hung Pan1, Ting-Chi Wang1, Po-Yuan Chen2 and Chin-Fang Cindy Shen2
    1National Tsing Hua University
    2Synopsys Taiwan Co., Ltd.
  • 4:10 PM~4:30 PM
    D7-3 On Reliability Hardening of FPGA based RO-PUF by using Regression Methodologies
    Asha K. A., Abhishek Patyal and Hung-Ming Chen, National Yang Ming Chiao Tung University
  • 4:30 PM~4:50 PM
    D7-4 Layout Hotspot Pattern Clustering Using a Density-based Approach
    Ciao-Syun Lin1, Pin-Yian Tsai2, Yan-Hsiu Liu2, Yi-Ting Li1, Yung-Chih Chen3 and Chun-Yao Wang1
    1National Tsing Hua University
    2United Microelectronics Corporation
    3National Taiwan University of Science and Technology
  • 4:50 PM~5:10 PM
    D7-5 Designing Constant-Timed Accelerators using High-Level Synthesis: A Case Study of ECG Biometric Authentication
    James Kuban and Tosiron Adegbija, University of Arizona

Thursday, April 20, 10:20 AM~12:35 PM Ballroom A
T9 Memory and Storage Technology

  • the photo of Speaker
    10:20 AM~10:55 AM
    T9-1 Advanced Materials Engineering Solutions to Address DRAM Scaling Challenges
    Sony Varghese, Applied Materials
  • 10:55 AM~11:15 AM
    T9-2 Design of High-RA STT-MRAM for Future Energy-Efficient In-Memory Computing
    Ming-Chun Hong1,2, Yi-Hui Su2, Guan-Long Chen2, Yu-Chen Hsin2, Yao-Jen Chang2, Kuan-Ming Chen2, Shan-Yi Yang2, I-Jung Wang2, SK Ziaur Rahaman2, Hsin-Han Lee2, Jeng-Hua Wei2, Shyh-Shyuan Sheu2, Wei-Chung Lo2, Shih-Chieh Chang2 and Tuo-Hung Hou1
    1National Yang Ming Chiao Tung University
    2Industrial Technology Research Institute
  • 11:15 AM~11:35 AM
    T9-3 Structure and Performance Co-optimization for the Development of Highly Reliable Spin-Orbit Torque Magnetic Random Access Memory
    Sk Ziaur Rahaman, Yu-Chen Hsin, Shan-Yi Yang, Yao-Jen Chang, Hsin-Han Lee, Kuan-Ming Chen, I-Jung Wang, Guan-Long Chen, Yi-Hui Su, Cheng-Yi Shih, Shih-Ching Chiu, Chih-Yao Wang, Jeng-Hua Wei, Shyh-Shyuan Sheu, Wei-Chung Lo, Duan-Li Deng and Shih-Chieh Chang
    Industrial Technology Research Institute
  • 11:35 AM~11:55 AM
    T9-4 Analysis of Monolithic 3D SRAM with Back-End-of-Line-compatible Transistors
    Yu-Cheng Lu, Ming Lee, Zi-Yuan Huang and Vita Pi-Ho Hu
    National Taiwan University
  • 11:55 AM~12:15 PM
    T9-5 Field Effect Depletion Regions exploiting different Qox polarities for Interface Passivation in High-Resistivity Silicon Substrates
    M.Moulin1, T. Fache1, M. Rack2, C. Plantier1, J. Lugo1, L. Hutin1 and J.-P. Raskin2
    2Université catholique de Louvain
  • 12:15 PM~12:35 PM
    T9-6 An Area and Energy Efficient All Resistive Neuromorphic-Computing Platform Implemented by a 4-bit-per-cell RG-FinFET Memory
    J. P. Wu1,2 , M. Y. Lee1, T. C . Kao1, Y. J. Li1, C. H. Liu2 , J. C. Guo1 and Steve S. Chung1
    1National Yang Ming Chiao Tung University
    2National Taiwan Normal University