Thursday, April 20, 10:20 AM~11:20 AM Ballroom D

D9 ： Enabling Practices of Silicon Life-cycle Management

• 
  10:20 AM~10:40 AM

  D9-1 Silicon Lifecycle Solutions for Scaling Challenges in Technology, Design and System
  

  Wu Yang, Siemens Digital Industries Software
  

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• 
  10:40 AM~11:00 AM

  D9-2 Improving Silicon Health and Operational Metrics at Each Phase of the Device Lifecycle
  

  Ting-Pu Tai, Synopsys
  

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• 
  11:00 AM~11:20 AM

  D9-3 Analysis of Vmin Variability in Complex Digital Logic via Post-Silicon Profiling
  

  Harry H. Chen, MediaTek Inc.
  

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Thursday, April 20, 11:30 AM~12:30 PM Ballroom D

D10 ： Cutting-Edge Computing Technologies from Purpose-Built Accelerators, Unified Memory Interfaces, to AI SoC Design Flows

• 
  11:30 AM~11:50 AM

  D10-1 Designing the Most Energy-Efficient Recommendation Inference Chip
  

  Joe Kao, NEUCHIPS Inc.
  

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• 
  11:50 AM~12:10 PM

  D10-2 Achieving Uniform Memory Read Distribution in Storage Class Memory
  

  Yu-Ming Chang, Wolley Inc.
  

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• 
  12:10 PM~12:30 PM

  D10-3 Exploring the Optimized AI SoC Design Flow
  

  Kevin Wei, Synopsys
  

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PAGE CONTENTS

• -D9 :
   Enabling Practices of Silicon Life-cycle Management
• -D10 :
   Cutting-Edge Computing Technologies from Purpose-Built Accelerators, Unified Memory Interfaces, to AI SoC Design Flows