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Tuesday, April 19, 12:50 PM~5:00 PM Ballroom D
T1 ： Poster Session

  • 12:50 PM~5:00 PM
    T1-1 Performance Evaluation of 3D Memory-Logic Hybrid Bond Stacking by RLC Delay Model for Edge Computing Applications
    C.-L. Chuang, C.-L. Lu, C.-M. Chen, S.-C. Lin, C.-H. Huang, and S.-Z. Chang
    Powerchip Semiconductor Manufacturing Corporation
  • 12:50 PM~5:00 PM
    T1-2 Demonstration of 64 Conductance States and Large Dynamic Range in Si-doped HfO2 FeFETs under Neuromorphic Computing Operations
    Yu-Yun Wang1, Kuang-Chi Wang1, Cheng-Hung Wu1, Ting-Yu Chang1, Nicolò Ronchi2, Kaustuv Banerjee2, Geert Van den Bosch2, Jan Van Houdt2, 3 and Tian-Li Wu1
    1National Yang Ming Chiao Tung University
    2imec
    3KU Leuven
  • 12:50 PM~5:00 PM
    T1-3 Analog and Logic Circuits Fabricated on a Wafer-Scale Two-Dimensional Semiconductor
    Xinyu Wang1, Xinyu Chen1, Jingyi Ma1, Honglei Chen1, Saifei Gou1, Xiaojiao Guo1, Ling Tong1, Yin Xia1, Zihan Xu2, Peng Zhou1, Chenjian Wu3, and Wenzhong Bao1
    1Fudan University
    2Shenzhen Six Carbon Technology
    3Soochow University
  • 12:50 PM~5:00 PM
    T1-4 A New Cascode Design with Enhanced Power gain and Bandwidth for Application in mm-Wave Amplifier
    Jinq-Min Lin, Adhi Cahyo Wijaya, and Jyh-Chyurn Guo
    National Yang Ming Chiao Tung University
  • 12:50 PM~5:00 PM
    T1-5 Statistical 3D Device Simulation of Full Fluctuations of Gate-All-Around Silicon Nanosheet MOSFETs at Sub-3-nm Technology Nodes
    Sekhar Reddy Kola, Yiming Li, Chieh-Yang Chen, and Min-Hui Chuang
    National Yang Ming Chiao Tung University
  • 12:50 PM~5:00 PM
    T1-6 AlInGaN GaN HEMTs With different GaN cap layer on Low Resistivity Silicon Substrate
    Hui-Yu Chen1, Po-Tsung Tu1, Po-Chun Yeh1, Pei-Jer Tzeng1, Shyh-Shyuan Sheu1, Chih-I Wu1, Indraneel Sanyal2, and Jen-Inn Chyi2
    1Industrial Technology Research Institute
    2National Central University
  • 12:50 PM~5:00 PM
    T1-7 Standby Bias Improves the Endurance in Ferroelectric Field Effect Transistors due to Fast Neutralization of Interface Traps
    Zheng Wang, Nujhat Tasneem, Jae Hur, Hang Chen, Shimeng Yu, Winston Chern, and Asif Khan
    Georgia Institute of Technology
  • 12:50 PM~5:00 PM
    T1-8 Tetravalent doping in hafnium-zirconium oxides to lower polarization switching voltage
    Kisung Chae1,2, Andrew C Kummel1, and Kyeongjae Cho2
    1University of California, San Diego
    2The University of Texas at Dallas
  • 12:50 PM~5:00 PM
    T1-9 Novel Bit-by-bit Repair to Demonstrate STT-MRAM as NV-RAM
    Cheng-Jye Liu, Chin-Hsi Lin, Kuan-Yu Chen, and Li-Che Chen
    NS-Poles Technology Corp.
  • 12:50 PM~5:00 PM
    T1-10 The Impact of Nano Device Parameters Variations and Scaling Strategy for High Frequency Performance Enhancement in Nanoscale CMOS
    Adhi Cahyo Wijaya, Jinq-Min Lin, and Jyh-Chyurn Guo
    National Yang Ming Chiao Tung University
  • 12:50 PM~5:00 PM
    T1-11 High-Resistivity Substrates with PN Interface Passivation in 22 nm FD-SOI
    M. Rack1, L. Nyssens1, M. Nabet1, C. Schwan2, Z. Zhao2, S. Lehmann2, T. Herrmann2, D. Henke2, A. Kondrat2, C. Soonekindt2, F. Koch2, T. Kache2, D. P. Kini2, O. Zimmerhackl2, F. Allibert3, C. Aulnette3, D. Lederer1, J.-P. Raskin1 
    1Université catholique de Louvain
    2GlobalFoundries
    3Soitec
  • 12:50 PM~5:00 PM
    T1-12 Deep Learning Approach to Modeling and Exploring Random Sources of Gate-All-Around Silicon Nanosheet MOSFETs
    Rajat Butola, Yiming Li, and Sekhar Reddy Kola
    National Yang-Ming Chiao Tung University
  • 12:50 PM~5:00 PM
    T1-13 A Low-Power Current Readout for 77K Cryo-CMOS Quantum Systems with In-Circuit Model Extraction and Embedded Leakage-Based Temperature Monitoring
    Xin-Kai Cheng, Tzu-Chieh Tung and Tsung-Heng Tsai
    National Chung Cheng University
  • 12:50 PM~5:00 PM
    T1-14 Investigation of Intrinsic Ferroelectric Switching induced Variation for Scaled FeFETs considering Limited Domain Number
    Yi-Chin Luo and Pin Su
    National Yang Ming Chiao Tung University
  • 12:50 PM~5:00 PM
    T1-15 Three-Zone Junction Termination Extensions for Improved Performance of Vertical GaN PN Diodes
    Yu Duan1, Piao Guanxi2, Kazutada Ikenaga2, Hiroki Tokunaga2, Shuuichi Koseki2, Mayank Bulsara3 and Patrick Fay1
    1University of Notre Dame
    2Taiyo Nippon Sanso
    3Matheson
  • 12:50 PM~5:00 PM
    T1-16 Investigation on selectively etched SiGe and Si surface for Gate-All-Around CMOS devices fabrication
    Wei-Yuan Chang1, Chun-Lin Chu1, Guang-Li Luo1, Yi-Shuo Huang2, Chun-Hsiung Lin2, Po-Jung Sung1, Yao-Jen Lee1, Shih-Hong Chen1, Bo-Yuan Chen1, Wen-Fa Wu1, and Wen-Kuan Yeh1
    1Taiwan Semiconductor Research Institute
    2National Yang Ming Chiao Tung University
  • 12:50 PM~5:00 PM
    T1-17 Sensitivity Analysis of Ferroelectric Junctionless Transistors for Non-volatile Memory Applications
    Manish Gupta1 and Vita Pi-Ho Hu2
    1Birla Institute of Technology and Science Pilani
    2National Taiwan University
  • 12:50 PM~5:00 PM
    T1-18 Effects of Channel Length on RF Performance of T-gate Poly-Si TFTs with Green Laser-Crystallized Channels
    C.-K. Lee1, P.-H. Yu1, Y.-J. Ye1, P.-W. Li1, K.-M. Chen2, G.-W. Huang2, and H.-C. Lin1
    1National Yang Ming Chiao Tung University
    2Taiwan Semiconductor Research Institute
  • 12:50 PM~5:00 PM
    T1-19 High density batch bonding technology for chiplet design
    Ang-Ying Lin, Yu-Min Lin, Tzu-Hsuan Ni, and Tao-Chih Chang
    Industrial Technology Research Institute
  • 12:50 PM~5:00 PM
    T1-20 Study of Carrier Scattering and Mobility in Monolayer MoTe2 and WTe2 by First-Principle Analysis
    Hsiu-Chi Pai1, and Yuh-Renn Wu1,2
    1National Taiwan University
    2Industrial Technology Research Institute
  • 12:50 PM~5:00 PM
    T1-21 Al2O3-HfO2 mixed high-k dielectrics for MIM decoupling capacitors in the BEOL
    Konstantinos Falidas1, Konstantin Mertens1, Raik Hoffmann1, Malte Czernohorsky1, and
    Johannes Heitmann2
    1Fraunhofer IPMS – Center Nanoelectronic Technologies
    2Technische Universität Bergakademie Freiberg
  • 12:50 PM~5:00 PM
    T1-22 Contacts to Two-dimensional Materials: Image Forces, Dielectric Environment, and Back-gate
    Madhuchhanda Brahma1, Maarten L. Van de Put1, Edward Chen2, Massimo V. Fischetti1, and William G. Vandenberghe1
    1The University of Texas at Dallas
    2Taiwan Semiconductor Manufacturing Company Ltd.,
  • 12:50 PM~5:00 PM
    T1-23 The Effect of Annealing Temperature on Antiferroelectric Zirconia
    Anthony A. Gaskell1, Zheng Wang1, Milan Dopita2, Dominik Kriegner2, Nujhat Tasneem1, and
    Asif I. Khan1
    1Georgia Institute of Technology
    2Charles University
  • 12:50 PM~5:00 PM
    T1-24 Evaluation of Multi-Finger PN-Body Tied SOI-FET -Origin and Suppression of Stepped Id-Vg Characteristics-
    Takayuki Mori, Kengo Nakata, and Jiro Ida
    Kanazawa Institute of Technology
  • 12:50 PM~5:00 PM
    T1-25 Crystalline Gallium Nitride Deposition by RF-Biased Atomic Layer Annealing
    Aaron J. McLeod1, Scott T. Ueda1, Jeff Spiegelman2, and Andrew C. Kummel1
    1University of California San Diego
    2Rasirc
  • 12:50 PM~5:00 PM
    T1-26 A Multi-Objective Approach for Rapid Identification of Post-Cu Interconnect Candidates
    Akash Ramdas, Evan Antoniuk, and Evan J Reed
    Stanford University
  • 12:50 PM~5:00 PM
    T1-27 A Nanosized-Metal-Grain Pattern-Dependent Model for Work-Function Fluctuation of Gate-All-Around Silicon Nanofin and Nanosheet MOSFETs
    Wen-Li Sung and Yiming Li
    National Yang Ming Chiao Tung University

Tuesday, April 19, 1:40 PM~3:20 PM Ballroom A
T2 ： Advanced Transistors for Logic and Security Applications

  • 1:40 PM~2:00 PM
    T2-1 Understanding Positive Bias Stability of a-InGaZnO Thin Film Transistors with HfO2 Gate Dielectric using Fast Measurement Techniques
    Qiwen Kong, Chen Sun, Zijie Zheng, Zuopu Zhou, Leming Jiao, Kaizhen Han, Yuye Kang, Jishen Zhang, Haiwen Xu, Yue Chen, and Xiao Gong
    National University of Singapore
  • 2:00 PM~2:20 PM
    T2-2 Fin-shape Optimization for Single Diffusion Break Device Performance in FinFET Technology
    Xiaoli He, Yuchen Du, Jianwei Peng, Hong Yu, Sangameshwar Rao Saudari, Jae Gon Lee, Owen Hu
    GlobalFoundries
  • 2:20 PM~2:40 PM
    T2-3 6 Stacked Ge0.95Si0.05 nGAAFETs without Parasitic Channels by Wet Etching
    Chun-Yi Cheng, Wan-Hsuan Hsieh, Bo-Wei Huang, Yi-Chun Liu, Chien-Te Tu, Chung-En Tsai, Shee-Jier Chueh, Guan-Hua Chen, and C. W. Liu
    National Taiwan University
  • 2:40 PM~3:00 PM
    T2-4 Self-Inhibit Complementary Cells by High-k Metal Gate Transistors for Physical Unclonable Function
    Wang-Yi Lee, Chang-Pei Yeh, Ya-Chin King, and Chrong Jung Lin
    National Tsing Hua University
  • 3:00 PM~3:20 PM
    T2-5 A Novel Physical Unclonable Function: NBTI-PUF Realized by Random Trap Fluctuation (RTF) Enhanced True Randomness in 14 nm FinFET Platform
    L. C. Lin1, E R. Hsieh2, T. C. Kao1, M. Y. Lee1, J. K. Chang1, J. C. Guo1, S.S. Chung1, T.P. Chen3, S.A. Huang3, T.J. Chen3, O. Cheng3
    1National Yang Ming Chiao Tung University
    2National Central University
    3United Microelectronics Corporation

Tuesday, April 19, 1:40 PM~3:35 PM Mezzanine A+B
T4 ： Ferrorelectric

  • the photo of Speaker
    1:40 PM~2:15 PM
    T4-1 Analog Matrix Computing with Resistive Memory: Circuits and Theory
    Zhong Sun, Peking University
    孫仲
  • 2:15 PM~2:35 PM
    T4-2 Ferroelectric-Gated GaN HEMTs for RF and mm-Wave Switch Applications
    Hansheng Ye, Chunlei Wu, Nivedhita Venkatesan, Jingshan Wang, Yu Cao, Andy Xie, Edward Beam, and Patrick Fay
    University of Notre Dame
  • 2:35 PM~2:55 PM
    T4-3 Impact of Stack Structure Control and Ferroelectric Material Optimization in Novel Laminate HSO and HZO MFMIS FeFET
    T. Ali, K. Mertens, R. Olivo, D. Lehninger, M. Lederer, F. Müller, M. Rudolph, S. Oehler, K. Kühnel, R. Hoffmann, P. Schramm, M. Czernohorsky, T. Kämpfe, and K. Seidel
    Fraunhofer Institute for Photonic Microsystems, Center Nanoelectronic Technologies
  • 2:55 PM~3:15 PM
    T4-4 Characterization of Double HfZrO2 based FeFET toward Low-Voltage Multi-Level Operation for High Density Nonvolatile Memory
    Z.-F. Lou1, C.-Y. Liao1, K.-Y. Hsiang1, 2, C.-Y. Lin1, Y.-D. Lin3, P.-C. Yeh3, C.-Y. Wang3, H.-Y. Yang3, P.-J. Tzeng3, T.-H. Hou2, 3, Y.-T. Tang4, and M. H. Lee1
    1National Taiwan Normal University
    2National Yang Ming Chiao Tung University
    3Industrial Technology Research Institute
    4National Central University
  • 3:15 PM~3:35 PM
    T4-5 Area Scalable Hafnium-Zirconium-Oxide Ferroelectric Capacitor Using Low-Temperature Back-End-of-Line Compatible 400℃ Annealing
    Tz-Shiuan Huang1,2, Po-Chun Yeh2, Hsin-Yun Yang2, Yu-De Lin2, Pei-Jer Tzeng2, Shyh-Shyuan Sheu2, Wei-Chung Lo2, Chih-I Wu2,3, and Tuo-Hung Hou1,2
    1National Yang Ming Chiao Tung University
    2Industrial Technology Research Institute
    3National Taiwan University

Tuesday, April 19, 3:55 PM~5:35 PM Mezzanine A+B
T5 ： Advanced Memory Technology (I)

  • 3:55 PM~4:15 PM
    T5-1 CeO2-Doped Hf0.5Zr0.5O2 Ferroelectrics for High Endurance Embedded Memory Applications
    Z. Yu1, B. Saini1, P.J. Liao2, Y.K. Chang2, V. Hou2, C.H. Nien2, Y.C. Shih2, S.H. Yeong2, V. Afanas’ev3, F. Huang1, J.D. Baniecki4, A. Mehta4, C.S. Chang2, H.-S.P. Wong1, W. Tsai1, P.C. McIntyre1,4
    1Stanford University
    2TSMC
    3University of Leuven, Leuven
    4SLAC National Accelerator Laboratory
  • 4:15 PM~4:35 PM
    T5-2 Cell Stability and Write Improvement of 2T (Footprint) Stacked SRAM
    Tao Chou, Chia-Che Chung, Hsin-Cheng Lin, and C. W. Liu
    National Taiwan University
  • 4:35 PM~4:55 PM
    T5-3 Development of Highly Manufacturable, Reliable, and Energy-Efficient Spin-Orbit Torque Magnetic Random Access Memory (SOT-MRAM)
    S. Z. Rahaman1, Y.-J. Chang1, Y.-C. Hsin1, S.-Y. Yang1, F.-M. Chen1, K.-M. Chen1,2, I-J. Wang1, H.-H. Lee1, G.-L. Chen1, Y.-H. Su1, C.-Y. Shih1, S.-C. Chiu1, J.-H. Wei1, S.-C. Yen3, K.-C. Huang3, C.-C. Chen3, M.-C. Chen3, S.-S. Sheu1, W.-C. Lo1, S.-Z. Chang3, Y.-C. See3, D.-L. Deng1, and C.-I Wu1,4
    1Industrial Technology Research Institute
    2National Yang Ming Chiao Tung University
    3Powerchip Semiconductor Manufacturing Corporation
    4National Taiwan University
  • 4:55 PM~5:15 PM
    T5-4 The Thermal Stability Improvement of Spin-orbit-torque (SOT) Devices with a Thin PtMn Insertion
    Yao-Jen Chang1, Fang-Ming Chen1, Kuan-Ming Chen1,3, Shan-Yi Yang1, Yu-Chen Hsin1, Sk Ziaur Rahaman1, I-Jung Wang1, Hsin-Han Lee1, Yi-Hui Su1, Guan-Long Chen1, Cheng-Yi Shih1, Shih-Ching Chiu1, Jeng-Hua Wei1, Shyh-Shyuan Sheu1, Wei-Chung Lo1, Yuan-Chieh Tseng3, Chih-Huang Lai4, Denny Tang1, Chih-I Wu1,2
    1Industrial Technology Research Institute
    2National Taiwan University
    3National Yang Ming Chiao Tung University
    4National Tsing Hua University
  • 5:15 PM~5:35 PM
    T5-5 Proposal & Demonstration of Low Current SOT-MRAM based on Brand New Mechanism for Retention Energy of Strain-Induced Magnetic Anisotropy
    Hiroaki Yoda1, Kay Yakushiji2, and Akio Fukushima2
    1Spin-Orbitronics Technologies, Inc.
    2National Institute of Advanced Industrial Science and Technology

Wednesday, April 20, 10:20 AM~12:15 PM Ballroom A
T6 ： Emerging Devices for AI

  • the photo of Speaker
    10:20 AM~10:55 AM
    T6-1 The Road to Fuse With and Beyond Silicon Circuits for 2D Materials
    Peng Zhou, Fudan University
    周鵬
  • 10:55 AM~11:15 AM
    T6-2 Anneal-Free HZO-Based Ferroelectric Field-Effect Transistor for Back-End-of-Line-Compatible Monolithic 3D Integration
    Shih-Hao Tsai, Chun-Kuei Chen, Xinghua Wang, Umesh Chand, Sonu Hooda, Evgeny Zamburg, and Aaron Voon-Yew Thean
    National University of Singapore
  • 11:15 AM~11:35 AM
    T6-3 Neuromorphic Computing with Fe-FinFETs in the Presence of Variation
    Sourav De1, Md. Aftab Baig1, Bo-Han Qiu1, Hoang-Hiep Le1, Yao-Jen Lee2, and Darsen Lu1
    1National Cheng Kung University
    2Taiwan Semiconductor Research Institute
  • 11:35 AM~11:55 AM
    T6-4 Pure CMOS embedded Artificial Synaptic Device (eASD) for High Density Neuromorphic Computing Chip
    Hsin-Yuan Yu1, Yao-Hung Huang1, Yue-Der Chih2, Jonathan Chang2, Ya-Chin King1, and Chrong Jung Lin1
    1National Tsing Hua University
    2Taiwan Semiconductor Manufacturing Company
  • 11:55 AM~12:15 PM
    T6-5 Improved Synaptic Characteristics in Bilayer Memristor by Post-Oxide Deposition Annealing for Pattern Recognition
    Dayanand Kumar1,2, Yi-Rong Huang2, Pratibha Pal1, Aftab Saleem2,Amit Singh3, Hoonkyung Lee4, Yeong-Her Wang1, and Tseung Yuen Tseng2
    1National Cheng Kung University
    2National Yang Ming Chiao Tung University
    3Academia Sinica
    4Konkuk University

Wednesday, April 20, 10:20 AM~12:00 PM Ballroom C
T8 ： Non-Fe Gate Stack & Interconnect

  • 10:20 AM~10:40 AM
    T8-1 A 12nm CMOS Technology on High Performance Multi-Workfunction Transistors
    Yuchen Du, Jianhua Yin, Xiaoli He, Hui Zhan, Hong Yu, Wen Zhi Gao, and Jae Gon Lee
    GlobalFoundries
  • 10:40 AM~11:00 AM
    T8-2 Dual Gate Oxide CMOS Process on 4H-SiC
    Bing-Yue Tsui, Chia-Lung Hung, Te-Kai Tsai, Li-Jung Lin, Ting-Wei Wang, and Po-Hung Chen
    National Yang Ming Chiao Tung University
  • 11:00 AM~11:20 AM
    T8-3 BEOL-Compatible, ALD-grown In2O3 Top-Gate FETs with Maximum Drain Current of 3 A/mm through Thermal Engineering and Pulse Measurement
    Pai-Ying Liao, Mengwei Si, Zhuocheng Zhang, Zehao Lin, and Peide. D. Ye
    Purdue University
  • 11:20 AM~11:40 AM
    T8-4 Lift-off Free Complementary Carbon Nanotube FETs Fabricated With Conventional Processing in a Silicon Foundry
    T. Srimani1, A.C. Yu1, B. Benton2, M. Nelson2, M.M. Shulaker1
    1Massachusetts Institute of Technology
    2Skywater Technology 
  • 11:40 AM~12:00 PM
    T8-5 The Development of Accurate Model Considering the Proximity Effect to Guide the BEoL Metal Scheme Design in the Advanced Logic Device
    Stanley S.-Y. Chang, W.-C. Kang, T.-H. Chang
    National Taiwan University

Thursday, April 21, 10:20 AM~12:35 PM Ballroom A
T10 ： RF, Analog, and Optical Sensing

  • the photo of Speaker
    10:20 AM~10:55 AM
    T10-1 Integration of Multimode Sensory and Data Processing in Single-Transistor Sensors
    Ming He, Peking University
    賀明
  • 10:55 AM~11:15 AM
    T10-2 Improved gm and RTN Device Performance using Thick SOI in 22FDX® for Analog Applications
    L. Pirro, A. Zaka, S. Morvan, O. Zimmerhackl, R. Nelluri, T. Hermann, M. Majer, H. Pagel, N. Wu, M. Otto and J. Hoentschel
    GlobalFoundries
  • 11:15 AM~11:35 AM
    T10-3 RF Performance Optimization of Stacked Si Nanosheet nFETs
    Hsin-Cheng Lin, Tao Chou, Kung-Ying Chiu, Chia-Che Chung, Chia-Jung Tsen, and C. W. Liu
    National Taiwan University
  • 11:35 AM~11:55 AM
    T10-4 Wide Temperature Range and High Thermal Sensitivity Radiometer Image Sensor Using CMOS SPAD Array
    Hui-Chen Tsai, Chun-Hsien Liu, Sheng-Di Lin, Chia-Ming Tsai, and Jau-Yang Wu
    National Yang Ming Chiao Tung University
  • 11:55 AM~12:15 PM
    T10-5 Si Metal-Oxide-Semiconductor and Si/SiGe Heterostructure Quantum Dots
    Yu-Jui Wu1, Chih-Ying Chiang1, Hung-Yu Tsao1, Tsung-Ying Li1, Tz-Ming Wang1, Min-Jui Lin1, Chia-You Liu1, Ching-Chen Yeh1, Cheng-Hsueh Yang1, Chi-Te Liang1, and Jiun-Yun Li1,2
    1National Taiwan University
    2Taiwan Semiconductor Research Institute
  • 12:15 PM~12:35 PM
    T10-6 2T-Pixel Sensors Array for on-Wafer in-Chamber DUV Sensing
    Wei-Hwa Lin, Chien-Ping Wang, Jiaw-Ren Shih, Chrong-Jung Lin,  and Ya-Chin King
    National Tsing Hua University

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