Tuesday, April 20, 12:50 PM~5:30 PM Ballroom C
T3 Poster Session

  • T3-1 A 500V SOI-LIGBT With Multiple Deep-Oxide Trenches For Fast Turn-OFF
    Yongjiu Cui, Jie Ma, Long Zhang, Jing Zhu, Weifeng Sun, Xinyu Liu, Wangming Cui, and Zhixiang Zhou
    Southeast University
  • T3-2 Back-Gate Network Extraction Free from Dynamic Self-Heating in FD SOI
    Lucas Nyssens, Martin Rack, Arka Halder, Martin Vanbrabant, Valeriya Kilchytska, and Jean-Pierre Raskin
    Université catholique de Louvain
  • T3-3 Suppressed Source-to-Drain Tunneling and Short-Channel Effects for MFIS-type InGaAs and Si Negative-Capacitance FinFETs
    Shih-En Huang and Pin Su
    National Chiao Tung University, Taiwan
  • T3-4 Benchmarking the Performance of Heterogeneous Stacked RRAM with CFET-SRAM and MRAM for Deep Neural Network Application Amidst Variation and Noise
    Parthasarathi Pal1, Sunanda Thunder2, Min-Jung Tsai1, Po-Tsang Huang2, and Yeong Her Wang1
    1National Cheng Kung University
    2National Chiao Tung University, Taiwan.
  • T3-5 Transfer Characteristics of CMOS Inverter using “Steep SS PN-Body Tied SOI-FET”
    Shota Ishiguro1, Jiro Ida1, Takayuki Mori1, and Koichiro Ishibashi2
    1Kanazawa Institute of Technology
    2The University of Electro-Communications
  • T3-6 Analysis of Drain Current Enhancement on “PN-Body Tied SOI-FET” 
    -Bulk vs Surface Conduction Mode and Low Vds Saturation Effect-

    Hiroki Ito1, Jiro Ida1, Takayuki Mori1, and Koichiro Ishibashi2
    1Kanazawa Institute of Technology
    2The University of Electro-Communications
  • T3-7 Calculation of Field Dependent Mobility in MoS2 and WS2with Multi-Valley Monte Carlo Method
    Pin-Fang Chen1, Yuh-Renn Wu1,2
    1National Taiwan University
    2Industrial Technology Research Institute
  • T3-8 Improved Switching Time in Negative Capacitance Junctionless Transistors
    Manish Gupta and Vita Pi-Ho Hu
    National Taiwan University
  • T3-9 Machine Learning Approach to Predicting Tunnel Field-Effect Transistors
    Chandni Akbar, Narasimhulu Thoti, and Yiming Li
    National Chiao Tung University, Taiwan
  • T3-10 A precise debugging method and defect diagnosis with mass big-data analysis in the designed high-dense array for rapid yield improvement in a logic platform
    Chan-Ching Lin1, Shenzhi-Yang Lin2, Ryan Liang1, Chi-Pei Lu1, Cheng-Shu Ho1, Chieh Lo1, Shao-Yu Hsu1, Jim-Chen Chen1, Fan Lan2, Weiwei Pan2, Sa Zhao2, Yongjun Zheng2, and Shou-Zen Chang1
    1Powerchip Semiconductor Manufacturing Corp.
    2Semitronix
  • T3-11 A Novel Design of Ferroelectric Nanowire Tunnel Field Effect Transistors
    Narasimhulu Thoti and Yiming Li
    National Chiao Tung University
  • T3-12 Ferroelectric Characterization in Ultrathin Hf0.5Zr0.5O2 MFIS Capacitors by Piezoresponse Force Microscopy (PFM) in Vacuum
    Cheng-Hung Wu1, Artur Useinov1, Tian-Li Wu1, and Chun-Jung Su2
    1National Chiao Tung University, Taiwan
    2Taiwan Semiconductor Research Institute
  • T3-13 Selective Area Epitaxy of Axial Wurtzite -InAs Nanowire on InGaAs NW by MOCVD
    Deepak Anandan, Edward Yi Chang, Hung Wei Yu, Hua Lun Ko, Venkatesan Nagarajan, and Sankalp Kumar Singh
    National Chiao Tung University, Taiwan
  • T3-14 Impact of Interfacial Layer on the Switching Characteristics of HZO-based Ferroelectric Tunnel Junction
    Haolin Li, Pengying Chang, Gang Du, Jinfeng Kang, and Xiaoyan Liu
    Peking University
  • T3-15 Alleviation of Charge Trapping and Flicker Noise in HfZrO2-Based Ferroelectric Capacitors by Thermal Engineering
    Sourav De1, Wei-Xuan Bu1, Bo-Han Qiu1, Chung-Jun Su2, Yao-Jen Lee2, and Darsen D. Lu1
    1National Cheng Kung University
    2Taiwan Semiconductor Research Institute
  • T3-16 Improvement of Nanotwinned Copper Thermal Stability for High Temperature Heterogeneous Integration
    Wei-Lan Chiu, Ying Tzu Hung, Ou-Hsiang Lee, Tsung Yu Ou-Yang, Hsiang-Hung Chang, and Wei-Chung Lo
    Industrial Technology Research Institute

Tuesday, April 20, 1:40 PM~3:55 PM Ballroom A
T1 Advanced CMOS Technology

  • 1:40 PM~2:15 PM
    T1-1 TBD

  • 2:15 PM~2:35 PM
    T1-2 FinFET Plus: A Scalable FinFET Architecture with 3D Air-Gap and Air-Spacer Toward the 3nm Generation and Beyond
    C. K. Chiang1, H. Pai1, J. L. Lin2, J. K. Chang1, M. Y. Lee1, E. R. Hsieh2, K. S. Li3, G. L. Luo3, Osbert Cheng4, and S. S. Chung1
    1National Chiao Tung University, Taiwan
    2National Central University
    3Taiwan Semiconductor Research Institute
    4United Microelectronics Corp
  • 2:35 PM~2:55 PM
    T1-3 The First Ge Nanosheets GAAFET CMOS Inverters Fabricated by 2D Ge/Si Multilayer Epitaxy, Ge/Si Selective Etching
    Chun-Lin Chu, Guang-Li Luo, Szu-Hung Chen, Wei-Yuan Chang, Wen-Fa Wu and Wen-Kuan Yeh
    Taiwan Semiconductor Research Institute, National Applied Research Laboratories
  • 2:55 PM~3:15 PM
    T1-4 Sub-60 mV/dec Germanium Nanowire Field-Effect-Transistors with 2-nm-thick Ferroelectric Hf0.5Zr0.5O2
    Y.-W. Lin1, T.-Y. Yu2, C.-J. Su2, Y.-N. Chen1, H.-H. Chang1, G.-L. Luo2, C.-T. Wu2, W.-F. Wu2, K.-L. Lin2, F.-J. Hou2, Y.-C. Wu1, and W.-K. Yeh2
    1National Tsing Hua University
    2Taiwan Semiconductor Research Institute
  • 3:15 PM~3:35 PM
    T1-5 The Powerful Methods of Flicker Noise Improvement in 22nm Technology
    Achilles Fang, Jen Wei Pan, Widson Wu, Sheng Cho, Wei Jun Chen, Jia Bin Yeh, Zhi Cheng Lee, You Ren Liu, Kai Lin Lee, Leonard Chen, Vincent Hsueh, S .W. Hsieh, Ta Kang Lo, Jakent Pai, Daniel Chen, Yao Chin Cheng, Steven Hsu, Osbert Cheng, and G. C. Hung
    United Microelectronics Corp.
  • 3:35 PM~3:55 PM
    T1-6 Si Cryo-CMOS and Quantum Dots for Quantum Computing Applications
    Yu-Jui Wu1, Chih-Ying Chiang1, Hung-Yu Tsao1, Min-Jui Lin1, Pu-Jia Hsieh1, Ching-Chen Yeh1, Wei-Ren Syong1, Kai-Syang Hsu1, Chi-Te Liang1, Jeng-Chung Chen2, and Jiun-Yun Li1,3
    1National Taiwan University
    2National Tsing-Hua University
    3Taiwan Semiconductor Research Institute, National Applied Research Laboratories

Tuesday, April 20, 1:40 PM~3:55 PM Mezzanine A+B
T4 Non-Volatile Memories

  • the photo of Speaker
    1:40 PM~2:15 PM
    T4-1 The Pursuit of Atomistic Switching and Cross Point Memory (Invited)
    DerChang Kau, Intel
  • 2:15 PM~2:35 PM
    T4-2 An 8kb spin-orbit-torque magnetic random-access memory
    Guan-Long Chen1, I-Jung Wang1, Po-Shao Yeh1, Sih-Han Li1, Shan-Yi Yang1, Yu-Chen Hsin1, Hsin-Tsun Wu1, HsuMing Hsiao1, Yao-Jen Chang1, Kuan-Ming Chen1,3, SK Ziaur Rahaman1, Hsin-Han Lee1, Yi-Hui Su1, Fang-Ming Chen1,
    Jeng-Hua Wei1, Shyh-Shyuan Sheu1, Chih-I Wu1,2, and Denny Tang1
    1Industrial Technology Research Institute
    2National Taiwan University
    3National Chiao Tung University
  • 2:35 PM~2:55 PM
    T4-3 Ultrahigh Spin-Orbit Torque Efficiency at Spin Reorientation Transition State in Pt/Co Multilayer
    Fen Xue1, Shy-Jay Lin2, Mahendra DC1, Chong Bi1, Xiang Li1, Wilman Tsai1, and Shan X. Wang1
    1Stanford University, US
    2Taiwan Semiconductor Manufacturing Company, Taiwan
  • 2:55 PM~3:15 PM
    T4-4 Multi-bit cryogenic flash memory on Si/SiGe and Ge/GeSi heterostructures
    Wei-Chih Hou1, Nai-Wen Hsu1, Hsiang-Shun Kao1, and Jiun-Yun Li1, 2
    1National Taiwan University
    2Taiwan Semiconductor Research Institute
  • 3:15 PM~3:35 PM
    T4-5 Bandgap-Engineered Tunneling Layer on Operation Characteristics of Poly-Ge Charge-Trapping Flash Memory Devices
    Jung-En Tsai, Kuei-Shu Chang-Liao, and Hsin-Kai Fang
    National Tsing Hua University
  • 3:35 PM~3:55 PM
    T4-6 A Twin Bit AND-Type Multiple-Time-Programming Memory Cell by Nano-scaled High–k Metal Gate Process
    Che-Wei Chu, Chrong Jung Lin, and Ya-Chin King
    National Tsing Hua University

Tuesday, April 20, 4:15 PM~5:55 PM Mezzanine A+B
T5 Oxide Transistors and BEOL/Process Technology

  • 4:15 PM~4:35 PM
    T5-1 BEOL Compatible Indium-Tin-Oxide Transistors: Switching of Ultra-High-Density 2D Electron Gas over 0.8×1014 /cm2 by Ferroelectric Polarization
    Mengwei Si, Zehao Lin, Junkang Li, Chang Niu, Xiao Lyu, Dongqi Zheng, and Peide D. Ye
    Purdue University
  • 4:35 PM~4:55 PM
    T5-2 Double-Layer Amorphous InGaZnO Thin Film Transistors with High Mobility and High Reliability
    Song-Ling Li1, Ming-Xuan Lee1, Chia-Chun Yen1, Tsang-Long Chen2, Cheng-Hsu Chou2, and C. W. Liu1
    1National Taiwan University
    2Innolux Corporation
  • 4:55 PM~5:15 PM
    T5-3 Grain Structure – Resistivity Relationship of Ru ALD Precursors
    Michael Breeden, Victor Wang, Francis Yu, and Andrew C. Kummel
    University of California, San Diego
  • 5:15 PM~5:35 PM
    T5-4 Asymmetry Low Temperature Cu-Polymer Hybrid Bonding with Au Passivation layer
    Ming-Wei Weng, Shan-Yu Mao, Demin Liu, Han-Wen Hu, Kuan-Neng Chen
    National Chiao Tung University
  • 5:35 PM~5:55 PM
    T5-5 On-Wafer Electronic Layer Detectors Array (ELDA) for e-beam Imaging in Advanced Lithographic Systems
    Chien-Ping Wang1, Burn Jeng Lin1, Jiaw-Ren Shih1, Yue-Der Chih2, Jonathan Chang2, Chrong Jung Lin1, and Ya-Chin King1
    1National Tsing Hua University
    2Taiwan Semiconductor Manufacturing Company

Wednesday, April 21, 10:20 AM~12:00 PM Ballroom C
T7 Power and RF Devices

  • 10:20 AM~10:40 AM
    T7-1 High Voltage Gain 4H-SiC CMOS Technology Featuring LOCal Oxidation of SiC (LOCOSiC) Isolation and Balanced Gate Dielectric
    Bing-Yue Tsui, Chia-Lung Hung, Ya-Ru Jhuang, Yi-Ting Huang, Jung-Chien Cheng, Fang-Hsin Lu, Yi-Ting Shih, Ya-Hsin Lee, Liang-Yu Chen, Fu-Hsiang Chuang, and Pei-Wen Li
    National Chiao Tung University
  • 10:40 AM~11:00 AM
    T7-2 CMOS-compatible GaN HEMT on 200mm Si-substrate for RF application
    Po-Chun Yeh1, Po-Tsung Tu1, Hsueh-Hsing Liu1, Chien-Hua Hsu1, Hsin-Yun Yang1, Yi-Keng Fu1, Li-Heng Lee1, Pei-Jer Tzeng1, Yuh-Renn Wu1,2, Shyh-Shyuan Sheu1, Wei-Chung Lo1, and Chih-I Wu1,2
    1Industrial Technology Research Institute
    2National Taiwan University
  • 11:00 AM~11:20 AM
    T7-3 Si MOSFETs with GaN-Drain for RF Power Applications
    Tien-Tung Luong1, Jessie Lin1, Jessie Chuang1, Jason Woo2, and Edward Yi Chang1
    1National Chiao Tung University, Taiwan
    2University of California, Los Angeles
  • 11:20 AM~11:40 AM
    T7-4 Superior High-Frequency Performance of T-Gated Poly-Si TFTs
    Y. A. Huang1, K. P. Peng1, H. C. Lin1, P. W. Li1, K. M. Chen2, and G. W. Huang2
    1National Chiao Tung University, Taiwan
    2Taiwan Semiconductor Research Institute
  • 11:40 AM~12:00 PM
    T7-5 FD-SOI mm-Wave Differential Single-Pole Switches with Ultra-High Isolation
    Martin Rack1, Lucas Nyssens1, Sidina Wane2, Damienne Bajon2, Dimitri Lederer1, and Jean-Pierre Raskin1
    1
    Université catholique de Louvain
    2eV-Technologies
     

Thursday, April 22, 10:20 AM~12:35 PM Ballroom A
T10 Ferroelectric FETs and Memories

  • the photo of Speaker
    10:20 AM~10:55 AM
    T10-1 Ferroelectric and Antiferroelectric materials (Invited)
    Dina Triyoso, Tokyo Electron Technology Center, America, LLC
  • 10:55 AM~11:15 AM
    T10-2 Current percolation path impacting switching behavior of ferroelectric FETs
    Franz Müller1, Maximilian Lederer1, Ricardo Olivo1, Tarek Ali1, Raik Hoffmann1, Halid Mulaosmanovic2, Sven Beyer3, Stefan Dünkel3, Johannes Müller3, Stefan Müller4, Konrad Seidel1, and Gerald Gerlach5
    1Fraunhofer IPMS-CNT
    2NaMLab gGmbH
    3GLOBALFOUNDRIES
    4Ferroelectric Memory GmbH
    5Technische Universität Dresden
  • 11:15 AM~11:35 AM
    T10-3 DFT Models of Ferroelectric Hafnium-Zirconium Oxide Stacks With and Without Dielectric Interlayers
    Kisung Chae1,2, Andrew Kummel1, Kyeongjae Cho2
    1University of California San Diego
    2The University of Texas at Dallas
  • 11:35 AM~11:55 AM
    T10-4 Ultra-thin Hf0.5Zr0.5O2 Ferroelectric Tunnel Junction with High Current Density
    Yueh-Hua Chu1, Hsin-Hui Huang1, Yu-Hao Chen1, Chien-Hua Hsu2, Pei-Jer Tzeng2, Shyh-Shyuan Sheu2, Wei-Chung Lo2, Chih-I Wu2,3, and Tuo-Hung Hou1,2
    1National Chiao Tung University, Taiwan
    2Industrial Technology Research Institute
    3National Taiwan University
  • 11:55 AM~12:15 PM
    T10-5 Three-dimensional (3D) Non-volatile SRAM with IWO Transistor and HZO Ferroelectric Capacitor
    Yuan-Chun Luo1, Suman Datta2, Shimeng Yu1
    1Georgia Institute of Technology
    2University of Notre Dame
  • 12:15 PM~12:40 PM
    T10-6 Comparison of 2-T FeFET Nonvolatile Memory Cells: Gate Select vs. Drain Select
    Bo-Kai Huang, Wei-Xiang You, and Pin Su
    National Chiao Tung University, Taiwan

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