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Registration
Tuesday, April 20, 1:40 PM~5:30 PM Ballroom B
J2
:
In-Memory Computing
1:40 PM~2:15 PM
J2-1
Challenges of Computation-in-Memory Circuits for AI Edge Applications
Meng-Fan (Marvin) Chang, TSMC/ National Tsing Hua University
張孟凡
View Biography
2:15 PM~2:50 PM
J2-2
Introduction of 3D AND-type Flash Memory and It's Applications to Computing-in-Memory (CIM)
Hang-Ting Lue, Macronix International Co., Ltd.
呂函庭
View Biography
2:50 PM~3:25 PM
J2-3
Neurocomputing and Neurooptimization with Stochastic Memristive Networks
Dmitri Strukov, University of California, Santa Barbara
View Biography
3:45 PM~4:20 PM
J2-4
Scalable RRAM-based in-memory Computing Design for Embedded AI
Wei D. Lu, University of Michigan
盧偉
View Biography
4:20 PM~4:55 PM
J2-5
Current Status and Issues of in-memory Accelerators for Deep Neural Networks
Jun Deguchi, Kioxia Corp.
View Biography
4:55 PM~5:30 PM
J2-6
Robust Model Mapping Optimization For Non-Ideal Computing In-Memory
Tian-Sheuan Chang, National Yang Ming Chiao Tung University
張添烜
View Biography
Wednesday, April 21, 10:20 AM~12:05 PM Ballroom B
J4-1
:
Design-Technology Co-Optimization and Advanced Packaging (I)
10:20 AM~10:50 AM
J4-1-1
Design/System Technology Co-Optimization for 3nm Node and Beyond
S.C. Song, Qualcomm
View Biography
10:50 AM~11:20 AM
J4-1-2
Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction Co-Optimization
Yarui Peng, University of Arkansas
View Biography
11:20 AM~11:50 AM
J4-1-3
Opportunities for 2.5/3D Heterogeneous SoC Integration
Iris Hui-Ru Jiang, National Taiwan University
江蕙如
View Biography
11:50 AM~12:05 PM
J4-1
Panel Discussion
Wednesday, April 21, 1:40 PM~3:25 PM Ballroom B
J4-2
:
Design-Technology Co-Optimization and Advanced Packaging (II)
1:40 PM~2:10 PM
J4-2-1
From Design to System-Technology optimization for CMOS
Julien Ryckaert, imec
View Biography
2:10 PM~2:40 PM
J4-2-2
Active Silicon Chiplet-Based Interposer for Exascale High Performance Computing
Séverine Chéramy, CEA-Leti
View Biography
2:40 PM~3:10 PM
J4-2-3
Self-Heating Effects from Transistors to Gates
Hussam Amrouch, University of Stuttgart
View Biography
3:10 PM~3:25 PM
J4-2
Panel Discussion
PAGE CONTENTS
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J2 :
In-Memory Computing
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J4-1 :
Design-Technology Co-Optimization and Advanced Packaging (I)
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J4-2 :
Design-Technology Co-Optimization and Advanced Packaging (II)
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