Tuesday, April 20, 1:40 PM~3:20 PM Ballroom D

D1 ： Mixed Signal Techniques

• 1:40 PM~2:00 PM

  D1-1 A Compact Thermal Sensor with Duty-Cycle Modulation on 1200 µm² in 7nm FinFET
  

  Matthias Eberlein and Harald Pretl, Johannes Kepler University Linz
• 2:00 PM~2:20 PM

  D1-2 An Adaptive Loop Gain Tracking Digital PLL Using Spectrum-Balancing Technique
  

  Guan-Yu Su, Zhi-Heng Kang and Shen-Iuan Liu, National Taiwan University
  
• 2:20 PM~2:40 PM

  D1-3 A Digital Phase-Locked Loop With Background Supply Noise Cancellation
  

  Yen-Min Tseng, Yu-Chi Yen and Shen-Iuan Liu, National Taiwan University
  
• 2:40 PM~3:00 PM

  D1-4 An 8-Bit 1.25-GS/s 2.5-GHz ERBW Folding-Subrange ADC with Power-Efficient Metastability Error Reduction Technique
  

  Bo-Wei Chen¹, Yung-Hui Chung² and Chia-Ming Tsai¹

  ¹ National Chiao Tung University

  ² National Taiwan University of Science and Technology 
• 3:00 PM~3:20 PM

  D1-5 A 677-μW 90-dB DR 16-kHz BW Incremental ΔΣ ADC for Sensor Interfaces
  

  Chia-Wei Kao, Che-Wei Hsu, Jia-Sheng Huang, Yu-Cheng Huang, Shih-Che Kuo and

  Chia-Hung Chen, National Chiao Tung University

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Tuesday, April 20, 3:40 PM~4:40 PM Ballroom D

D2 ： Digital Circuit Techniques for Security and In-Memory Computing

• 3:40 PM~4:00 PM

  D2-1 A Reliable Near-Threshold Voltage SRAM-Based PUF
  

  Lih-Yih Chiou, Chi-Ray Huang and Jing-Yu Huang, National Cheng Kung University
  
• 4:00 PM~4:20 PM

  D2-2 A Reconfigurable In-SRAM Computing Architecture for DCNN Applications
  

  Yu-Hsien Lin, Chi Liu, Chia-Lin Hu, Kang-Yu Chang and Shyh-Jye Jou, National Chiao Tung University
  
• 4:20 PM~4:40 PM

  D2-3 Machine Learning Assisted Challenge Selection for Modeling Attack Resistance in Strong PUFs
  

  Sying-Jyan Wang and Tzu-Heng Chang, National Chung Hsing University
  

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Wednesday, April 21, 1:40 PM~3:00 PM Ballroom C

D4 ： Power Management

• 1:40 PM~2:00 PM

  D4-1 Shutdown mode implementation for Boost and Inverting Buck-Boost converter 
  

  Venkatesh G Kadlimatti and Sumit Bhat, Sankalp Semiconductor Pvt Ltd.
  
• 2:00 PM~2:20 PM

  D4-2 A Hybrid Supply Modulator for 10-MHz LTE Power Amplifier with 17.3% PAE Improvement
  

  Yen-Ting Chen, Mao-Ling Chiu, Hou-Wei Teng and Tsung-Hsien Lin, National Taiwan University
  
• 2:20 PM~2:40 PM

  D4-3 A 6.78MHz Wireless Power Transfer System with Maximum Power Tracking over Wide Load Range
  

  You-Xin Ling and Tsung-Heng Tsai, National Chung Cheng University
  
• 2:40 PM~3:00 PM

  D4-4 Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit Against False Trigger During Fast Power-ON Events
  

  Han-Sheng and Ming-Dou Ker, National Chiao Tung University
  

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Wednesday, April 21, 1:40 PM~3:00 PM Ballroom D

D5 ： Emerging Techniques on EDA and Testing

• 1:40 PM~2:00 PM

  D5-1 A Test Method for Large-size TSV Considering Resistive Open Fault and Leakage Fault Coexistence
  

  Hao Chang¹, Yong Xu¹ and Tianming Ni²

  ¹Anhui University of Finance and Economics 

  ²Anhui Polytechnic University 
• 2:00 PM~2:20 PM

  D5-2 Chip Performance Prediction Using Machine Learning Techniques
  

  Min-Yan Su¹, Wei-Chen Lin¹, Yen-Ting Kuo¹, Chien-Mo Li¹, Eric Jia-Wei Fang² and

  Sung S.-Y. Hsueh²

  ¹ National Taiwan University

  ² MediaTek Inc.
• 2:20 PM~2:40 PM

  D5-3 Storage-Aware Scheduling Algorithm for Reservoir
  Switching Minimization on Digital Microfluidic Biochips
  

  Ling-Yen Song, Chih-Shen Yeh, Chien-Nan Liu and Juinn-Dar Huang
  National Chiao Tung University
  
• 2:40 PM~3:00 PM

  D5-4 An Approach to the Vehicle Routing Problem with Balanced Pick-up Using Ising Machines
  

  Siya Bao¹, Masashi Tawada¹, Shu Tanaka² and Nozomu Togawa¹

  ¹ Waseda University

  ² Keio University

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Wednesday, April 21, 3:20 PM~4:20 PM Ballroom C

D6 ： System and Architecture Design for Smart Data Analytics

• 3:20 PM~3:40 PM

  D6-1 Reconfigurable Database Processor for Query Acceleration on FPGA
  

  Bo-En Chen, Bo-Yen Lin and Bo-Cheng Lai, National Chiao Tung University
• 3:40 PM~4:00 PM

  D6-2 Dynamic Mapping Mechanism to Compute DNN Models on a Resource-limited NoC Platform
  

  Kun-Chih Chen, Chun-Chuan Wang, Cheng-Kang Tsai and Jing-Wen Liang

  National Sun Yat-sen University
• 4:00 PM~4:20 PM

  D6-3 Embedded Bearing Fault Detection Platform Design for the Drivetrain
  System in the Future Industry 4.0 Era
  

  Kun-Chih Chen, Jing-Wen Liang, Yueh-Chi Yang, Jo-Chiao Ku, Jui-Cheng Wang and Hsiang-Ling Tai

  National Sun Yat-sen University

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Wednesday, April 21, 4:40 PM~5:40 PM Ballroom C

D8 ： AI Applications

• 4:40 PM~5:00 PM

  D8-1 Gait Parameters Analysis Based on Leg-and-shoe-mounted IMU and Deep Learning
  

  Po-Hsin Lin, Chang-Lin Shih, Davy P. Y. Wong and Pai H. Chou, National Tsing Hua University
  
• 5:00 PM~5:20 PM

  D8-2 Design of 2D Systolic Array Accelerator for Quantized Convolutional Neural Networks
  

  Chia-Ning Liu, Yu-An Lai and Chih-Hung Kuo, National Cheng Kung University
• 5:20 PM~5:40 PM

  D8-3 Learning Based Placement Refinement to Reduce DRC Short Violations
  

  Ying-Yao Huang¹, Chang-Tzu Lin², Wei-Lun Liang² and Hung-Ming Chen¹

  ¹ National Chiao Tung University

  ² Industrial Technology Research Institute

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PAGE CONTENTS

• -D1 :
   Mixed Signal Techniques
• -D2 :
   Digital Circuit Techniques for Security and In-Memory Computing
• -D4 :
   Power Management
• -D5 :
   Emerging Techniques on EDA and Testing
• -D6 :
   System and Architecture Design for Smart Data Analytics
• -D8 :
   AI Applications