Thursday, April 22, 10:20 AM~11:20 AM Ballroom D
D10 Area of AI Accelerators, Design Methodology and Hardware Software Co-design

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    10:20 AM~10:40 AM
    D10-1 ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design
    Shu-Ming Liu, Skymizer Taiwan Inc.
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    10:40 AM~11:00 AM
    D10-2 Intelligence Everywhere: The Challenges and Opportunities for Semiconductor Designs
    Pin-Han Chen, NEUCHIPS Corp.
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    11:00 AM~11:20 AM
    D10-3 A TinyMLaaS Ecosystem for Machine Learning in IoT: Overview and Research Challenges
    Hiroshi Doyu, Ericsson

Thursday, April 22, 11:30 AM~12:30 PM Ballroom D
D11 Parallel AI Processing and Chiplets

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    11:30 AM~11:50 AM
    D11-1 Flexible Acceleration of Data Processing with RISC-V DSP, Vector and Custom Extensions
    Charlie Hong-Men Su, Andes Technology Corp.
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    11:50 AM~12:10 PM
    D11-2 Tensor-Centric Processor Architecture for Applications in Advanced Driver Assistance Systems
    Yu-Sheng Lin, Inventec Inc.
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    12:10 PM~12:30 PM
    D11-3 Opportunity and Challenge of Chiplet-Based HPC and AIoT
    Jie-Wei Lai, Spreadtrum Communications (former)