Best Paper Award
Starting 2009, an Award Committee is formed for the selection of the Best Paper Award each year. The selection criteria of the award include the technical contents and writing quality of the paper as well as the quality of the presentation at the symposium. The award will be presented to the selected paper in the following year's symposium.
2021 VLSI-DAT Best Paper Award Committee
Led by the Technical Program Committee co-chairs, Prof. Atsushi Takahashia, Dr. Racy Cheng and Prof. Chung-Ho Chen, the award committee members consist of subcommittee chairs and co-chairs. The Award Committee will select the 2021 Best Paper Award based on the criteria including the technical contents and depth, quality of the paper as well as the quality of the presentation. The award will be announced after the conference and granted in the VLSI-TSA and VLSI-DAT Opening ceremony in 2022. The winner will be rewarded by a certificate and US$500 . Besides, it will also offer the registration fee waived of 2022 VLSI-DAT.
2020 Award Winners Congratulations !
The 2020 Best Paper Award will be granted in the VLSI-DAT Opening ceremony in 2021 and the winner will be rewarded by a certificate and US$500 . Besides, it will also offer the registration fee waived of 2021 VLSI-DAT.
• A 500nW-50µW Indoor Photovoltaic Energy Harvester with Multi-mode MPPT
Co-authors: Ming-Chia Chang, Min-Hsuan Wu and Shen-Iuan Liu National Taiwan University
• Low-Active-Energy and Low-Standby-Power Sub-threshold ROM for IoT Edge Sensing Systems
Co-authors: Jinn-Shyan Wang, Chien-Tung Liu and Chao-Hsiang Wang
National Chung Cheng University
2021 Best Paper Award Candidates
The 2021 Best Paper Award will be granted in the VLSI-DAT Opening ceremony in 2022 and the winner will be rewarded by a certificate and US$500. Besides, it will also offer the registration fee waived of 2022 VLSI-DAT.
• D1-2 An Adaptive Loop Gain Tracking Digital PLL Using Spectrum-Balancing Technique
Co-authors: Guan-Yu Su, Zhi-Heng Kang and Shen-Iuan Liu
National Taiwan University
• D2-1 A Reliable Near-Threshold Voltage SRAM-Based PUF
Co-authors: Lih-Yih Chiou, Jing-Yu Huang, Chi-Kuan Li and Chen-Chung Tsai
National Cheng Kung University
• D5-2 Chip Performance Prediction Using Machine Learning Techniques
Co-authors: Min-Yan Su, Wei-Chen Lin, Yen-Ting Kuo, Chien-Mo Li, Eric Jia-Wei Fang and Sung S.-Y. Hsueh
National Taiwan University
• D5-3 Storage-Aware Scheduling Algorithm for Reservoir Switching Minimization on Digital
Co-authors: Ling-Yen Song, Chih-Shen Yeh, Chien-Nan Liu and Juinn-Dar Huang
National Chiao Tung University
• D6-2 Dynamic Mapping Mechanism to Compute DNN Models on a Resource-limited NoC Platform
Co-authors: Kun-Chih Chen, Chun-Chuan Wang, Cheng-Kang Tsai and Jing-Wen Liang
National Sun Yat-sen University
• D8-1 Gait Parameters Analysis Based on Leg-and-shoe-mounted IMU and Deep Learning
Co-authors: Po-Hsin Lin, Chang-Lin Shih, Davy P. Y. Wong and Pai H. Chou
National Tsing Hua University