Best Paper Award
Starting 2009, an Award Committee is formed for the selection of the Best Paper Award each year. The selection criteria of the award include the technical contents and writing quality of the paper as well as the quality of the presentation at the symposium. The award will be presented to the selected paper in the following year's symposium.
2019 VLSI-DAT Best Paper Award Committee
Led by the Technical Program Committee co-chairs, Prof. Hidetoshi Onodera and Prof. Juinn-Dar Huang, the award committee members consist of subcommittee chairs and co-chairs. The Award Committee will select the 2019 Best Paper Award based on the criteria including the technical contents and depth, quality of the paper as well as the quality of the presentation.The award will be announced after the conference and granted in the VLSI-TSA and DAT Opening ceremony in 2020. The winner will be rewarded by a certificate and US$500 . Besides, it will also offer the registration fee waived of 2020 VLSI-DAT.
2018 Award Winners Congratulations !
The 2018 Best Paper Award will be granted in the VLSI-DAT Opening ceremony in 2019 and the winner will be rewarded by a certificate and US$500 . Besides, it will also offer the registration fee waived of 2019 VLSI-DAT.
• A 1.86mJ/Gb/Query Bit-Plane Payload Machine Learning Processor in 90nm CMOS
Co-authors: Fang-Ju Ku, Tung-Yu Wu, Yen-Chin Liao, Hsie-Chia Chang, Wing Hung Wong and Chen-Yi Lee
National Chiao Tung University
•
Using Range-equivalent Circuits for Facilitating Bounded Sequential Equivalence Checking
Co-authors: Yung-Chih Chen, Wei-An Ji, Chih-Chung Wang, Ching-Yi Huang, Chia-Cheng Wu, Chia-Chun Lin
and Chun-Yao Wang
National Tsing Hua University
2019 Candidates of Best Paper Award
• D2-2: An Analog Front-End Circuit for CO2 Sensor Readout in 0.18-μm CMOS Process
Co-authors: Deng-Kai Lin, Chih-Chan Tu, Shih-Kai Kuo and Tsung-Hsien Lin
National Taiwan University
• D2-3: A Power-efficient, Bi-directional Readout Interface Circuit for Cyclic-voltammetry
Electrochemical Sensors
Co-authors: Yi-Chia Chen, Shao-Yung Lu, Jui-Hsiang Tsai and Yu-Te Liao
National Chiao Tung University
• D9-1: A 50 Gb/s Adaptive ADFE with SNR Based Power Management for 2-PAM Systems
Co-authors: Chee-Kit Ng, Yu-Chun Lin and Shyh-Jye Jou
National Chiao Tung University
• D5-1: A Lightweight 1.16 pJ/bit Processor for the Authenticated Encryption Scheme KetjeSR
Co-authors: Yun-Wen Lu1, Antoon Purnal2, Simon Vandenhende2, Chen-Yi Lee1, Ingrid Verbauwhede2
and Hsie-Chia Chang1
1National Chiao Tung University
2K.U.Leuven, Belgium
• D6-1: Reactant Minimization for Multi-Target Sample Preparation on Digital Microfluidic
Biochips using Network Flow Models
Co-authors: Kang-Yi Fan1, Shigeru Yamashita2 and Juinn-Dar Huang1
1National Chiao Tung University
2Ritsumeikan University
• D11-3: TEMPO: Thermal-Efficient Management of Power in High-Throughput Network Switches
Co-authors: Tom Munk1, Hillel Kugler2, Ofir Maori1 and Adam Teman2
1Mellanox Technologies
2Bar-Ilan University
• D8-1: Efficient Write Scheme for Algorithm-based Multi-ported Memory
Co-authors: Bo-Ya Chen, Bo-En Chen and Bo-Cheng Lai
National Chiao Tung University
• D1-4: Primitive Concept Identification in A Given Set of Wafer Maps
Co-authors: Ahmed Wahba1, Chuanhe Shan1, Li-C. Wang1 and Nik Sumikawa2
1University of South Carolina Beaufort
2NXP
• D11-2: Event-Driven Model for High Speed End-to-End Simulation of Transmission System
with Non-linear Optical Elements and Cascaded Clock-and-Data Recovery Circuits
Co-authors: Jun Matsui and Hisakatsu Yamaguchi
Fujitsu Laboratories LTD.