Tuesday, April 23, 1:30 PM~3:10 PM Ballroom A

T1 ： RRAM & NAND

• 1:30 PM~1:50 PM

  T1-1 Twin-Bit Resistive Random Access Memory in FinFET CMOS Logic Technologies
  

  Chieh Lee, Yu-Ting Hung, Cheng-Jun Lin, Ya-Chin King and Chrong Jung Lin

  National Tsing Hua University

• 1:50 PM~2:10 PM

  T1-2 Hot-Carrier Injection-Induced Disturb and Improvement Methods in 3D NAND Flash Memory
  

  Wei-Liang Lin¹, Wen-Jer Tsai¹, C.C. Cheng¹, Chun-Chang Lu¹, S.H. Ku¹, Y.W. Chang¹, Wei Wu¹, Lenvis Liu¹, S.W. Hwang¹, Tao-Cheng Lu¹, Kuang-Chao Chen¹, Tseung-Yuen Tseng² and Chih-Yuan Lu¹

  ¹MXIC

  ²NCTU

• 2:10 PM~2:30 PM

  T1-3 High Density NV-SRAM Using Memristor and Selector as Technology Assist
  

  Sai Subrahmanya Teja Nibhanupudi and Jaydeep P. Kulkarni

  University of Texas at Austin

• 2:30 PM~2:50 PM

  T1-4 The Impact of Forming Temperature and Voltage on the Reliability of Filamentary RRAM
  

  Guan-Yu Chen¹, F.M. Lee¹, Y.Y. Lin¹, P.H. Tseng¹, K.C. Hsu¹, D.Y. Lee¹, M.H. Lee¹, H.L. Lung¹, K.Y. Hsieh¹, K.C. Wang¹, C.Y. Lu¹ and W.C. Wu²

  ¹Macronix International Co., Ltd. 

  ²National Tsing-Hua University (NTHU)

• 2:50 PM~3:10 PM

  T1-5 Stochastic Filament Formation on the Cycling Endurance of Backfilled Contact Resistive Random Access Memory Cells
  

  Yun-Feng Kao, Chrong Jung Lin and Ya-Chin King

  National Tsing Hua University 

      

---

Tuesday, April 23, 1:30 PM~6:30 PM Ballroom D

T3 ： Poster Session

• T3-1 A New Variability Source for Nanosheet GAA Transistors for sub-7nm Nodes
  

  Harsha Vardhan Penugonda, Swaroop Ganguly and Udayan Ganguly

  IIT Bombay

• T3-2 Impact of Multi-Domain Interaction on ON-State Characteristics of MFIS-Type 2D Negative-Capacitance FETs
  

  Po-Sheng Lu, Chia-Chen Lin and Pin Su

  National Chiao Tung University

• T3-3 Accurate Measurement of Sneak Current in ReRAM Crossbar Array with Data Storage Pattern Dependencies
  

  Yaqi SHANG and Takashi OHSAWA

  Waseda University

• T3-4 Selective Etching of Native Silicon Oxide in Preference to Silicon Oxide and Silicon
  

  Christopher Ahles¹, Jong Choi¹, Raymond Hung², Namsung Kim², Srinivas Nemani² and Andrew Kummel¹

  ¹University of California, San Diego

  ²Applied Materials

• T3-5 Enhancing IGZO Thin Film Transistor Scalability Through Tunneling Contact
  

  Zichao Ma¹, Xintong Zhang¹, Clarissa Prawoto¹, Lining Zhang², Longyan Wang³ and Mansun Chan¹

  ¹Hong Kong University of Science and Technology

  ²Shenzhen University
  ³Visionox

• T3-6 Cell Array Design with Row-Driven Source Line in Block Shunt Architecture Applicable to Future 6F2 1T1MTJ Memory
  

  Tongshuang HUANG and Takashi OHSAWA

  Waseda University

• T3-7 Evaluation of 2D Negative-Capacitance FETs for Low-Voltage SRAM Applications
  

  Kuei-Yang Tseng, Wei-Xiang You and Pin Su

  National Chiao Tung University

• T3-8 Analysis of Transient Effect on Super-Steep SS PN-Body Tied SOI-FET
  

  Takayuki Mori, Jiro Ida and Hiroki Endo

  Kanazawa Institute of Technology

• T3-9 A Large Dynamic Range Current Sensor Using Magnetic Tunnel Junction on 8” Si process line
  

  D.Y. Wang, I.J.Wang, C.S. Lin, J.W. Su, H.H. Lee, Y.C. Hsin, S.Y. Yang, Y.J. Chang, Y.C. Kuo, Y.H. Su, S.Z. Rahaman, G.L Chen, S.H. Li, J.H. Wei, K.C. Huang and C.I. Wu

  ITRI

• T3-10 Architecture Evaluation for Standalone and Embedded 1T-DRAM
  

  Md. Hasan Raza Ansari¹, Nupur Navlakha¹, Jyi-Tsong Lin² and Abhinav Kranti¹

  ¹Indian Institute of Technology Indore

  ²National Sun Yat-Sen University

• T3-11 TIPS-Pentacene:PS Blend Organic Field-Effect Transistors with Hybrid Gate Dielectric on Paper Substrate
  

  Vivek Raghuwanshi, Deepak Bharti, Ajay Kumar Mahato, Ishan Varun and Shree Prakash Tiwari

  Indian Institute of Technology,Jodhpur

• T3-12 Origin of fixed charges and dipole in GeOx/Al2O3 gate stack based on Ge
  

  Lixing Zhou, Xiaolei Wang, Xueli Ma, Jinjuan Xiang, Chao Zhao, Tianchun Ye and Wenwu Wang

  Institute of Microelectronics of Chinese Academy of Sciences 

• T3-13 Contradiction Behaviors between I-V and C-V Curves after Self-Heating Stress in a-IGZO TFT with Triple-Stacked Channel Layers
  

  Yu-Ching Tsao, Mao-Chou Tai and Ting-Chang Chang

  National Sun-Yat-Sen University 

• T3-14 Defect Localization and Electrical Fault Isolation for Metal Connection using Helium Ion Microscope
  

  Deying Xia, Shawn McVey and Wilhelm Kuehn

  Carl Zeiss SMT

• T3-15 Thermal Atomic Layer Etching of Amorphous and Crystalline Hafnium Oxide, Zirconium Oxide, and Hafnium Zirconium Oxide
  

  Jessica A. Murdzek and Steven M.George

  University of Colorado

• T3-16 Thermal Stability of Shallow Ge N+-P Junction with Thin GeSn Top Layer
  

  Hsiu-Hsien Liao, Yi-Ju Chen and Bing-Yue Tsui

  National Chiao Tung University 

• T3-17 Selective Atomic Layer Deposition of TiO2
  

  Christopher Ahles¹, Jong Choi¹, Keith Wong², Srinivas Nemani² and Andrew Kummel¹

  ¹University of California, San Diego

  ²Applied Materials

---

Wednesday, April 24, 10:20 AM~12:45 PM Ballroom A

T5 ： MRAM

• 
  10:20 AM~12:45 PM

  T5-1 Can Magnetic Memory (MRAM) Displace DRAM?
  

  Denny Tang

  Western Digital Corporation, USA 

• 
  10:20 AM~12:45 PM

  T5-2 Interfacial Engineering of SOT-MRAM to Modulate Atomic Diffusion and Enable PMA Stability
  

  Shan Xiang Wang

  Stanford University, USA

• 
  10:20 AM~12:45 PM

  T5-3 Computational Random Access Memory (CRAM) and Applications
  

  Jian-Ping Wang

  University of Minnesota, USA

• 12:05 PM~12:25 PM

  T5-4 Comprehensive Reliability Study of STT-MRAM Devices and Chips for Last Level Cache Applications (LLC) at 0x Nodes
  

  Jian Zhu, Yuan-Jen Lee, Huanlong Liu, Son Le, Jodi Iwata-Harms, Sahil Patel, Ru-Ying Tong, Vignesh Sundar, Santiago Serrano-Guisan, Dongna Shen, Renren He, Jesmin Haq, Jeffrey Teng, Vinh Lam, Yi Yang, Yu-Jen Wang, Tom Zhong, Luc Thomas, Hideaki Fukuzawa, Guenole Jan and Po-Kang Wang

  Headway Technologies, Inc.

• 12:25 PM~12:45 PM

  T5-5 Spin-orbit Torque Driven One-bit Magnetic Racetrack Devices – Memory and Neuromorphic Applications
  

  See-Hun Yang, Chirag Garg, Timothy Phung, Charles Rettner and Brian Hughes 

  IBM Research - Almaden

---

Wednesday, April 24, 10:20 AM~12:15 PM Ballroom B

T6 ： Ferroelectric/NCFET

• 
  10:20 AM~10:55 AM

  T6-1 Device Structural Effects, SPICE Modeling and Circuit Evaluation for Negative-Capacitance FETs
  

  Pin Su,

  National Chiao Tung University, Taiwan 

• 10:55 AM~11:15 AM

  T6-2 Ferroelectric Si-doped HfO2 Capacitors for Next-Generation Memories
  

  Ava J. Tan¹, Zhongwei Zhu², Hwan Sung Choe², Chenming Hu¹, Sayeef Salahuddin¹ and Alex Yoon²

  ¹UC Berkeley

  ²Lam Research Corporation

   

• 11:15 AM~11:35 AM

  T6-3 The Guideline on Designing a High Performance NC MOSFET by Matching the Gate Capacitance and Mobility Enhancement
  

  Y. C. Luo¹, F. L. Li¹, E. R. Hsieh¹, C. H. Liu¹, Steve Chung¹, T. P. Chen², S. A. Huang², T. J. Chen² and O. Cheng²

  ¹NCTU

  ²UMC 

• 11:35 AM~11:55 AM

  T6-4 Impact of Gate Stack Design on Improving Subthreshold Swing Behaviors in Ferroelectric-Gate Field-Effect Transistors
  

  Shinji Migita¹, Hiroyuki Ota¹, Akira Toriumi² and Takashi Matsukawa¹

  ¹AIST

  ²The University of Tokyo

• 11:55 AM~12:15 PM

  T6-5 Fabrication of Ω-gated Negative Capacitance FinFETs and SRAM
  

  P.-J. Sung and Yao-Jen Lee

  National Nano Device Laboratories

---

Wednesday, April 24, 10:20 AM~12:35 PM Ballroom C

T7 ： Processing

• 
  10:20 AM~10:55 AM

  T7-1 Electron Enhanced Atomic Layer Deposition (EE-ALD)
  

  Steven George

  University of Colorado Boulder, USA 

• 10:55 AM~11:15 AM

  T7-2 Analytical Estimation of LER Like Variability in GAA Nano-sheet Transistors
  

  First:Amita, Ajinkya Gorad and Udayan Ganguly

  IIT Bombay

• 11:15 AM~11:35 AM

  T7-3 Low Temperature Junctionless Device Stacking Enabled by Leading Edge Sequential 3D Integration
  

  Guillaume BESNARD¹, Gweltaz GAUDIN¹, Walter SCHWARZENBACH¹, Ludovic ECARNOT¹, Ionut RADU¹, Bich-Yen NGUYEN¹, Anne VANDOOREN² and Nadine COLLAERT²

  ¹SOITEC S.A.

  ²IMEC vzw.

• 11:35 AM~11:55 AM

  T7-4 New Observation and Analysis of Layout Dependent Effects in Sub-40nm Multi-Ring and Multi-Finger nMOSFETs for High Frequency Applications
  

  Zu-Cheng Li, Jyh-Chyurn Guo and Jinq-Min Lin

  National Chiao Tung University

• 11:55 AM~12:15 PM

  T7-5 Backside Si Passivation: Leading to High Performance UTB GeOI Structures for Monolithic 3D Integrations
  

  Wen Hsin Chang, Toshifumi Irisawa, Hiroyuki Ishii, Noriyuki Uchida and Tatsuro Maeda

  AIST

• 12:15 PM~12:35 PM

  T7-6 Hyper-Selective Co Metal ALD on Metals vs. SiO2 Without Passivation
  

  Steven Wolf, Mike Breeden, Scott Ueda and Andrew Kummel

  University of California San Diego

---

Wednesday, April 24, 1:30 PM~3:30 PM Ballroom A

T8 ： Transistor

• 1:30 PM~1:50 PM

  T8-1 Novel Fine-Grain Back-Bias Assist Techniques for 14nm FDSOI Top-Tier SRAMs integrated in 3D-Monolithic
  

  Daphnée Bosch^1,2, François Andrieu¹, Lorenzo Ciampolini^1,3, Adam Makosiej¹, Olivier Weber^1,3, Xavier Garros¹, Joris Lacord¹, Jacques Cluzel¹, Eduardo Esmanhotto¹, Marco antonio Rios¹, Simon Lang¹, Bastien Giraud¹, Remy Berthelon³, Gérald Cibrario¹, Laurent Brunet¹, Perrine Batude¹, Claire Fenouillet-Béranger¹, Didier Lattard¹, Jean-Pierre Colinge¹, Francis Balestra² and Maud Vinet¹

  ¹CEA-LETI,

  ²IMEP-LAHC

  ³STMicroelectronics

• 1:50 PM~2:10 PM

  T8-2 Novel Vertically-Stacked Tensily-Strained Ge0.85Si0.15 GAA n-Channels on a Si Channel with SS=76mV/dec, DIBL=36mV/V, and Ion/Ioff=1.2E7
  

  Yu-Shiang Huang, Fang-Liang Lu, Hung-Yu Ye, Ya-Jui Tsou, Yi-Chun Liu, Chien-Te Tu and C. W. Liu

  National Taiwan University

• 2:10 PM~2:30 PM

  T8-3 The First GeSn Gate-All-Around Nanowire P-FET on the GeSnOI Substrate with Channel Length of 20 nm and Subthreshold Swing of 74 mV/decade
  

  Yuye Kang¹, Kaizhen Han¹, Eugene Y.-J. Kong¹, Dian Lei¹, Shengqiang Xu¹, Ying Wu¹, Yi-Chiau Huang² and Xiao Gong¹

  ¹National University of Singapore

  ²Applied Materials

• 2:30 PM~2:50 PM

  T8-4 Comparison of Vertically Double Stacked Poly-Si Nanosheet Junctionless Field Effect Transistors with Gate-all-around and Multi-gate Structure
  

  Meng-Ju Tsai, Kang-Hui Peng, Yu-Ru Lin and Yung-Chun Wu

  National Tsing Hua University

• 3:10 PM~3:30 PM

  T8-5 Virtual Source based I-V Model for Cryogenic CMOS Devices
  

  Hazem Elgabra¹, Brandon Buonacorsi¹, Christopher Chen², Jeff Watt², Jonathan Baugh¹ and Lan Wei¹

  ¹The University of Waterloo

  ²Intel Programmable Solutions Group
  

---

Thursday, April 25, 10:20 AM~12:50 PM Ballroom B

T11 ： Novel Computing

• 
  10:20 AM~10:55 AM

  T11-1 Designing and Modeling Analog Neural Network Training Accelerators
  

  Sapan Agarwal

  Sandia National Laboratories, USA

• 10:55 AM~11:15 AM

  T11-3 Temporal Matrix-Matrix Multiplication with HfOx-Based RRAM Crossbar Array
  

  Zheng Zhou, Yizhou Zhang, Peng Huang, Yulin Feng, Runze Han, Lifeng Liu, Xiaoyan Liu and Jinfeng Kang

  Peking University

• 11:15 AM~11:35 AM

  T11-4 Full Memory Encryption With Magnetoelectric In-Memory Computing
  

  Albert Lee and Kang -L. Wang

  UCLA

• 11:35 AM~11:55 AM

  T11-5 Integrated Photonics of Transistor Laser, Detector and Active Load for All Optical NOR Gate
  

  Ardy Winoto, Junyi Qiu, Dufei Wu, Yu-Ting Peng and Milton Feng

  University of Illinois

• 11:55 AM~12:15 PM

  T11-6 A Novel RRAM Based Watermark Technique Utilizing the Impact of Forming Conditions on Reset Distribution
  

  Yachuan Pang, Huaqiang Wu, Bin Gao, Bohan Lin, He Qian

  Tsinghua university

---

PAGE CONTENTS

• -T1 :
   RRAM & NAND
• -T3 :
   Poster Session
• -T5 :
   MRAM
• -T6 :
   Ferroelectric/NCFET
• -T7 :
   Processing
• -T8 :
   Transistor
• -T11 :
   Novel Computing