email Contact

Tuesday, April 23, 4:10 PM~5:50 PM Ballroom A
T2 ： RRAM and NAND

  • 4:10 PM~4:30 PM
    T2-1 Twin-Bit Resistive Random Access Memory in FinFET CMOS Logic Technologies
    Chieh Lee, Yu-Ting Hung, Cheng-Jun Lin, Ya-Chin King and Chrong Jung Lin
    National Tsing Hua University
  • 4:30 PM~4:50 PM
    T2-2 Hot-Carrier Injection-Induced Disturb and Improvement Methods in 3D NAND Flash Memory
    Wei-Liang Lin1, Wen-Jer Tsai1, C.C. Cheng1, Chun-Chang Lu1, S.H. Ku1, Y.W. Chang1, Wei Wu1, Lenvis Liu1, S.W. Hwang1, Tao-Cheng Lu1, Kuang-Chao Chen1, Tseung-Yuen Tseng2 and Chih-Yuan Lu1
    1MXIC
    2NCTU
  • 4:50 PM~5:10 PM
    T2-3 High density NV-SRAM using memristor and selector as technology assist
    Sai Subrahmanya Teja Nibhanupudi and Jaydeep P. Kulkarni
    University of Texas at Austin
  • 5:10 PM~5:30 PM
    T2-4 The Impact of Forming Temperature and Voltage on the Reliability of Filamentary RRAM
    Guan-Yu Chen1, F.M. Lee1, Y.Y. Lin1, P.H. Tseng1, K.C. Hsu1, D.Y. Lee1, M.H. Lee1, H.L. Lung1, K.Y. Hsieh1, K.C. Wang1, C.Y. Lu1 and M.C. Wu2
    1Macronix International Co., Ltd. 
    2National Tsing-Hua University 
  • 5:30 PM~5:50 PM
    T2-5 Stochastic Filament Formation on the Cycling Endurance of Backfilled Contact Resistive Random Access Memory Cells
    Yun-Feng Kao, Chrong Jung Lin and Ya-Chin King
    National Tsing Hua University 
        

Tuesday, April 23, 1:30 PM~6:30 PM Ballroom D
T3 ： Poster Session

  • T3-1 A Variability Source for Nanosheet GAA Transistors for sub-7nm Nodes
    Harsha Vardhan Penugonda, Swaroop Ganguly and Udayan Ganguly
    IIT Bombay
  • T3-2 Impact of Multi-Domain Interaction on ON-State Characteristics of MFIS-Type 2D Negative-Capacitance FETs
    Po-Sheng Lu, Chia-Chen Lin and Pin Su
    National Chiao Tung University
  • T3-3 Accurate Measurement of Sneak Current in ReRAM Crossbar Array with Data Storage Pattern Dependencies
    Yaqi SHANG and Takashi OHSAWA
    Waseda University
  • T3-4 Selective Etching of Native Silicon Oxide in Preference to Silicon Oxide and Silicon
    Christopher Ahles1, Jong Choi1, Raymond Hung2, Namsung Kim2, Srinivas Nemani2 and Andrew Kummel1
    1University of California, San Diego
    2Applied Materials
  • T3-5 Enhancing IGZO Thin Film Transistor Scalability Through Tunneling Contact
    Zichao Ma1, Xintong Zhang1, Clarissa Prawoto1, Lining Zhang2, Longyan Wang3 and Mansun Chan1
    1Hong Kong University of Science and Technology
    2Shenzhen University
    3Visionox
  • T3-6 Cell Array Design with Row-Driven Source Line in Block Shunt Architecture Applicable to Future 6F2 1T1MTJ Memory
    Tongshuang HUANG and Takashi OHSAWA
    Waseda University
  • T3-7 Evaluation of 2D Negative-Capacitance FETs for Low-Voltage SRAM Applications
    Kuei-Yang Tseng, Wei-Xiang You and Pin Su
    National Chiao Tung University
  • T3-8 Analysis of Transient Effect on Super-Steep SS PN-Body Tied SOI-FET
    Takayuki Mori, Jiro Ida and Hiroki Endo
    Kanazawa Institute of Technology
  • T3-9 A Large Dynamic Range Current Sensor Using Magnetic Tunnel Junction on 8” Si process line
    D.Y. Wang, I.J.Wang, C.S. Lin, J.W. Su, H.H. Lee, Y.C. Hsin, S.Y. Yang, Y.J. Chang, Y.C. Kuo, Y.H. Su, S.Z. Rahaman, G.L Chen, S.H. Li, J.H. Wei, K.C. Huang and C.I. Wu
    ITRI
  • T3-10 Architecture Evaluation for Standalone and Embedded 1T-DRAM
    Md. Hasan Raza Ansari1, Nupur Navlakha1, Jyi-Tsong Lin2 and Abhinav Kranti1
    1Indian Institute of Technology Indore
    2National Sun Yat-Sen University
  • T3-11 TIPS-Pentacene:PS Blend Organic Field-Effect Transistors with Hybrid Gate Dielectric on Paper Substrate
    Vivek Raghuwanshi, Deepak Bharti, Ajay Kumar Mahato, Ishan Varun and Shree Prakash Tiwari
    Indian Institute of Technology,Jodhpur
  • T3-12 Origin of fixed charges and dipole in GeOx/Al2O3 gate stack based on Ge
    Lixing Zhou, Xiaolei Wang, Xueli Ma, Jinjuan Xiang, Chao Zhao, Tianchun Ye and Wenwu Wang
    Institute of Microelectronics of Chinese Academy of Sciences 
  • T3-13 Contradiction Behaviors between I-V and C-V Curves after Self-Heating Stress in a-IGZO TFT with Triple-Stacked Channel Layers
    Yu-Ching Tsao, Mao-Chou Tai and Ting-Chang Chang
    National Sun-Yat-Sen University 
  • T3-14 Defect Localization and Electrical Fault Isolation for Metal Connection using Helium Ion Microscope
    Deying Xia, Shawn McVey and Wilhelm Kuehn
    Carl Zeiss SMT
  • T3-15 Thermal Atomic Layer Etching of Amorphous and Crystalline Hafnium Oxide, Zirconium Oxide, and Hafnium Zirconium Oxide
    Jessica A. Murdzek and Steven M.George
    University of Colorado
  • T3-16 Thermal Stability of Shallow Ge N+-P Junction with Thin GeSn Top Layer
    Hsiu-Hsien Liao, Yi-Ju Chen and Bing-Yue Tsui
    National Chiao Tung University 
  • T3-17 Selective Atomic Layer Deposition of TiO2
    Christopher Ahles1, Jong Choi1, Keith Wong2, Srinivas Nemani2 and Andrew Kummel1
    1University of California, San Diego
    2Applied Materials

Wednesday, April 24, 10:20 AM~12:45 PM Ballroom A
T5 ： MRAM

  • the photo of Speaker
    10:20 AM~10:55 AM
    T5-1 Can Magnetic Memory (MRAM) Displace DRAM?
    Denny Tang
    Western Digital Corporation, USA 
  • the photo of Speaker
    10:55 AM~11:30 AM
    T5-2 Interfacial engineering of SOT-MRAM to modulate atomic diffusion and enable PMA stability >400 ◦C
    Shan Xiang Wang
    Stanford University, USA
  • the photo of Speaker
    11:30 AM~12:05 PM
    T5-3 Computational Random Access Memory (CRAM) and Applications
    Jian-Ping Wang
    University of Minnesota, USA
  • 12:05 PM~12:25 PM
    T5-4 Comprehensive Reliability Study of STT-MRAM Devices and Chips for Last Level Cache Applications (LLC) at 0x Nodes
    Jian Zhu, Yuan-Jen Lee, Huanlong Liu, Son Le, Jodi Iwata-Harms, Sahil Patel, Ru-Ying Tong, Vignesh Sundar, Santiago Serrano-Guisan, Dongna Shen, Renren He, Jesmin Haq, Jeffrey Teng, Vinh Lam, Yi Yang, Yu-Jen Wang, Tom Zhong, Luc Thomas, Hideaki Fukuzawa, Guenole Jan and Po-Kang Wang
    Headway Technologies, Inc.
  • 12:25 PM~12:45 PM
    T5-5 Spin-orbit torque driven one-bit magnetic racetrack devices – memory and neuromorphic applications
    See-Hun Yang, Chirag Garg, Timothy Phung, Charles Rettner and Brian Hughes 
    IBM Research - Almaden

Wednesday, April 24, 10:20 AM~12:15 PM Ballroom B
T6 ： Ferroelectric/NCFET

  • the photo of Speaker
    10:20 AM~10:55 AM
    T6-1 Device Structural Effects, SPICE Modeling and Circuit Evaluation for Negative-Capacitance FETs
    Pin Su,
    National Chiao Tung University, Taiwan 
  • 10:55 AM~11:15 AM
    T6-2 Ferroelectric Si-doped HfO2 Capacitors for Next-Generation Memories
    Ava J. Tan1, Zhongwei Zhu2, Hwan Sung Choe2, Chenming Hu1, Sayeef Salahuddin1 and Alex Yoon2
    1UC Berkeley
    2Lam Research Corporation
     
  • 11:15 AM~11:35 AM
    T6-3 The Guideline on Designing a High Performance NC MOSFET by
    Y. C. Luo1, F. L. Li1, E. R. Hsieh1, C. H. Liu1, Steve Chung1, T. P. Chen2, S. A. Huang2, T. J. Chen2 and O. Cheng2
    1NCTU
    2UMC 
  • 11:35 AM~11:55 AM
    T6-4 Impact of Gate Stack Design on Improving Subthreshold Swing Behaviors in Ferroelectric-Gate Field-Effect Transistors
    Shinji Migita1, Hiroyuki Ota1, Akira Toriumi2 and Takashi Matsukawa1
    1AIST
    2The University of Tokyo
  • 11:55 AM~12:15 PM
    T6-5 Fabrication of Ω-gated Negative Capacitance FinFETs and SRAM

    P.-J. Sung1,3, C.-J. Su1, D. D. Lu2, S.-X. Luo2, K.-H. Kao2, J.-Y. Ciou2, C.-Y. Jao4, H.-S. Hsu4, C.-J. Wang1, T.-C. Hong3, T.-H. Liao4, C.-C. Fang4, Y.-S. Wang2, H.-F. Huang2, J.-H. Li2, Y.-C. Huang3, F.-K. Hsueh1,3, C.-T. Wu1, Y.-C. Huang3, W. C.-Y. Ma4, K.-P. Huang5, Y.-J. Lee1, T.-S. Chao3, J. -Y. Li6, W.-F. Wu1, W.-K. Yeh1 and Y.-H. Wang7

    1National Nano Device Laboratories
    2National Cheng Kung University
    3National Chiao Tung University
    4National Sun Yat-Sen University
    5Industrial Technology Research Institute
    6National Taiwan University
    7National Applied Research Laboratories

Wednesday, April 24, 10:20 AM~12:35 PM Ballroom C
T7 ： Processing

  • the photo of Speaker
    10:20 AM~10:55 AM
    T7-1 Electron Enhanced Atomic Layer Deposition (EE-ALD)
    Steven George
    University of Colorado Boulder, USA 
  • 10:55 AM~11:15 AM
    T7-2 Analytical Estimation of LER-like Variability in GAA Nano-Sheet Transistors
    Amita, Ajinkya Gorad and Udayan Ganguly
    IIT Bombay
  • 11:15 AM~11:35 AM
    T7-3 Low temperature junctionless device stacking enabled by leading edge sequential 3D integration
    Guillaume BESNARD1, Gweltaz GAUDIN1, Walter SCHWARZENBACH1, Ludovic ECARNOT1, Ionut RADU1, Bich-Yen NGUYEN1, Anne VANDOOREN2 and Nadine COLLAERT2
    1SOITEC S.A.
    2IMEC vzw.
  • 11:35 AM~11:55 AM
    T7-4 New Observation and Analysis of Layout Dependent Effects in Sub-40nm Multi-Ring and Multi-Finger nMOSFETs for High Frequency Applications
    Zu-Cheng Li, Jyh-Chyurn Guo and Jinq-Min Lin
    National Chiao Tung University
  • 11:55 AM~12:15 PM
    T7-5 Backside Si passivation: leading to high performance UTB GeOI structures for monolithic 3D integrations
    Wen Hsin Chang, Toshifumi Irisawa, Hiroyuki Ishii, Noriyuki Uchida and Tatsuro Maeda
    AIST
  • 12:15 PM~12:35 PM
    T7-5 Hyper-Selective Co Metal ALD on Metals vs. SiO2 Without Passivation
    Steven Wolf, Mike Breeden, Scott Ueda and Andrew Kummel
    University of California San Diego

Wednesday, April 24, 1:30 PM~3:30 PM Ballroom A
T8 ： Transistor

  • 1:30 PM~1:50 PM
    T8-1 Novel Fine-Grain Back-Bias Assist Techniques for 14nm FDSOI Top-Tier SRAMs integrated in 3D-Monolithic
    Daphnée Bosch1,2, François Andrieu1, Lorenzo Ciampolini1,3, Adam Makosiej1, Olivier Weber1,3, Xavier Garros1, Joris Lacord1, Jacques Cluzel1, Eduardo Esmanhotto1, Marco antonio Rios1, Simon Lang1, Bastien Giraud1, Remy Berthelon3, Gérald Cibrario1, Laurent Brunet1, Perrine Batude1, Claire Fenouillet-Béranger1, Didier Lattard1, Jean-Pierre Colinge1, Francis Balestra2 and Maud Vinet1
    1CEA-LETI,
    2IMEP-LAHC
    3STMicroelectronics
  • 1:50 PM~2:10 PM
    T8-2 Novel Vertically-Stacked Tensily-Strained Ge0.85Si0.15 GAA n-Channels on a Si Channel with SS=76mV/dec, DIBL=36mV/V, and Ion/Ioff=1.2E7
    Yu-Shiang Huang, Fang-Liang Lu, Hung-Yu Ye, Ya-Jui Tsou, Yi-Chun Liu, Chien-Te Tu and C. W. Liu
    National Taiwan University
  • 2:10 PM~2:30 PM
    T8-3 The First GeSn Gate-All-Around Nanowire P-FET on the GeSnOI Substrate with Channel Length of 20 nm and Subthreshold Swing of 74 mV/decade
    Yuye Kang1, Kaizhen Han1, Eugene Y.-J. Kong1, Dian Lei1, Shengqiang Xu1, Ying Wu1, Yi-Chiau Huang2 and Xiao Gong1
    1National University of Singapore
    2Applied Materials
  • 2:30 PM~2:50 PM
    T8-4 Comparison of Vertically Double Stacked Poly-Si Nanosheet Junctionless Field Effect Transistors with Gate-all-around and Multi-gate Structure
    Meng-Ju Tsai, Kang-Hui Peng, Yu-Ru Lin and Yung-Chun Wu
    National Tsing Hua University
  • 2:50 PM~3:10 PM
    T8-5 Virtual Source based I-V Model for Cryogenic CMOS Devices
    Hazem Elgabra1, Brandon Buonacorsi1, Christopher Chen2, Jeff Watt2, Jonathan Baugh1 and Lan Wei1
    1The University of Waterloo
    2Intel Programmable Solutions Group
  • 3:10 PM~3:30 PM
    T8-6 Core-shell TFET Developments and TFET Limitations
    M. Passlack1, P. Ramvall1, T. Vasen1, A. Afzalian1, C. Thelander2,
    K.A. Dick2, L.-E. Wernersson2, G. Doornbos1 and M. Holland1
    1TSMC Corporate Research, Belgium
    2Lund University, Sweden

Thursday, April 25, 10:20 AM~11:55 AM Ballroom B
T11 ： Novel Computing

  • the photo of Speaker
    10:20 AM~10:55 AM
    T11-1 Designing and Modeling Analog Neural Network Training Accelerators
    Sapan Agarwal
    Sandia National Laboratories, USA
  • 10:55 AM~11:15 AM
    T11-2 Full Memory Encryption With Magnetoelectric In-Memory Computing
    Albert Lee and Kang -L. Wang
    UCLA
  • 11:15 AM~11:35 AM
    T11-3 Integrated Photonics of Transistor Laser, Detector and Active Load for All Optical NOR Gate
    Ardy Winoto, Junyi Qiu, Dufei Wu, Yu-Ting Peng and Milton Feng
    University of Illinois at Urbana-Champaign
  • 11:35 AM~11:55 AM
    T11-4 A Novel RRAM Based Watermark Technique Utilizing the Impact of Forming Conditions on Reset Distribution
    Yachuan Pang, Huaqiang Wu, Bin Gao, Bohan Lin and He Qian
    Tsinghua University

PAGE CONTENTS

Top

Copyright © 2019 VLSI TSA