Tuesday, April 17, 1:30 PM~5:20 PM Ballroom B
J3 Design and Technology Co-Optimization

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    1:30 PM~2:05 PM
    J3-1 Analysis of Thermal Effects in Integrated Radio Transmitters
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    1:30 PM~5:30 PM
    J3-3 Systematic Co-Optimization From Chip Design, Process Technology To Systems For GPU AI Chip And Autonomous Vehicles SOC
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    2:05 PM~2:40 PM
    J3-2 Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic pathfinding DTCO of advanced transistors
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    3:35 PM~4:10 PM
    J3-4 Machine Learning for IC Design and Technology Co-Optimization in Extreme Scaling
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    4:10 PM~4:45 PM
    J3-5 Abundant-Data Computing: The N3XT 1,000X
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    4:45 PM~5:20 PM
    J3-6 Co-designed systems for deep learning hardware accelerators

Wednesday, April 18, 1:30 PM~5:20 PM Ballroom B
J6 Technology and Design Challenges for Next Generation Communication

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    1:30 PM~2:05 PM
    J6-1 Antenna-in-Package Design and Module Integration for Millimeter-Wave Communication and 5G
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    2:05 PM~2:40 PM
    J6-2 Emerging Technologies and Concepts for 5G Applications
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    2:40 PM~3:15 PM
    J6-3 GaN-based digital transmitter architectures for 5G
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    3:35 PM~4:10 PM
    J6-4 5G mmWave communication: from system concept to implementation
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    4:10 PM~4:45 PM
    J6-5 Phased array technique for mm-wave wireless communication
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    4:45 PM~5:20 PM
    J6-6 Massive MIMO Detection VLSI Design

Tuesday, April 17, 3:10 PM~5:30 PM Ballroom A
T2 Application of FET/Integration Technologies to Bio-sensing

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    3:10 PM~3:45 PM
    T2-1 High-Mobility Polymer Field-Effect Transistor Based-Sensor Array for Selective Discrimination between Multiple Isomers
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    3:45 PM~4:20 PM
    T2-2 Integrated Molecule Recognition Sensor Electronics using Nanostrcured Metal Oxide on Silicon
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    4:20 PM~4:55 PM
    T2-3 Nanomechanical Sensors with AI towards Standard Olfactory IoT Sensing System
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    4:55 PM~5:30 PM
    T2-4 On the Detection, Characterization, and Identification of Single Molecule with Nanopores

Wednesday, April 18, 10:20 AM~12:05 PM
T5 Ferroelectrics on Si Technology

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    10:20 AM~10:55 AM
    T5-1 Hafnium oxide based ferroelectric devices for memories and beyond
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    10:55 AM~11:30 AM
    T5-2 Negative Capacitance Transistors
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    11:30 AM~12:05 PM
    T5-3 Device physics, design and challenge of Negative Capacitance FET

Wednesday, April 18, 3:30 PM~5:45 PM Ballroom A
T8 Future Patterning Solutions

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    3:30 PM~4:05 PM
    T8-1 Stochastic Limitations to EUV Lithography
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    4:05 PM~4:40 PM
    T8-2 Novel Patterning schemes and technologies for the sub 5nm era
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    4:40 PM~5:15 PM
    T8-3 Approaches and opportunities for area-selective atomic layer deposition
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    5:15 PM~5:45 PM
    T8-4 Highly CMOS-compatible & Cost-efficient Patterning with Tilted-ion Implantation

Thursday, April 19, 10:20 AM~12:40 PM Ballroom A
T9 Magnetic Materials & Memory

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    10:20 AM~10:55 AM
    T9-1 STT-MRAM for embedded memory applications from eNVM to Last Level Cache
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    10:55 AM~11:30 AM
    T9-2 Novel nanopatterning approach and improvements in STT-MRAM stacks for high density memory operation
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    11:30 AM~12:05 PM
    T9-3 Voltage-Control Spintronics Memory Having Potentials for High-Density and High-Speed Applications
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    12:05 PM~12:40 PM
    T9-4 The potential of nonvolatile magneto-electric devices for spintronic applications

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