Tuesday, April 17, 1:30 PM~5:20 PM Ballroom B

J3 ： Design and Technology Co-Optimization

• 
  1:30 PM~2:05 PM

  J3-1 Analysis of Thermal Effects in Integrated Radio Transmitters
  

  Christian Fager

  Chalmers University of Technology, Sweden 

• 
  1:30 PM~5:30 PM

  J3-3 Systematic Co-Optimization From Chip Design, Process Technology To Systems For GPU AI Chip And Autonomous Vehicles SOC
  

  John Hu

  NVIDIA, USA

• 
  2:05 PM~2:40 PM

  J3-2 Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic pathfinding DTCO of advanced transistors
  

  Stanley Seungchul Song

  Qualcomm, USA

• 
  3:35 PM~4:10 PM

  J3-4 Machine Learning for IC Design and Technology Co-Optimization in Extreme Scaling
  

  David Z. Pan

  University of Texas at Austin, USA

• 
  4:10 PM~4:45 PM

  J3-5 Abundant-Data Computing: The N3XT 1,000X
  

  Subhasish Mitra

  Stanford University, USA

• 
  4:45 PM~5:20 PM

  J3-6 Co-designed systems for deep learning hardware accelerators
  

  David M. Brooks

  Harvard University, USA

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Wednesday, April 18, 1:30 PM~5:20 PM Ballroom B

J6 ： Technology and Design Challenges for Next Generation Communication

• 
  1:30 PM~2:05 PM

  J6-1 Antenna-in-Package Design and Module Integration for Millimeter-Wave Communication and 5G
  

  Xiaoxiong Gu

  IBM, USA 

• 
  2:05 PM~2:40 PM

  J6-2 Emerging Technologies and Concepts for 5G Applications
  

  Wolfgang Bösch

  Graz University of Technology, Austria 

• 
  2:40 PM~3:15 PM

  J6-3 GaN-based digital transmitter architectures for 5G
  

  Florian Hühn

  FBH-Berlin, Germany

• 
  3:35 PM~4:10 PM

  J6-4 5G mmWave communication: from system concept to implementation
  

  Chih-Yuan Lin

  MediaTek, Taiwan

• 
  4:10 PM~4:45 PM

  J6-5 Phased array technique for mm-wave wireless communication
  

  Chien-Nan Kuo

  National Chiao Tung University, Taiwan

• 
  4:45 PM~5:20 PM

  J6-6 Massive MIMO Detection VLSI Design
  

  Chia-Hsiang Yang

  National Taiwan University, Taiwan

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Tuesday, April 17, 3:10 PM~5:30 PM Ballroom A

T2 ： Application of FET/Integration Technologies to Bio-sensing

• 
  3:10 PM~3:45 PM

  T2-1 High-Mobility Polymer Field-Effect Transistor Based-Sensor Array for Selective Discrimination between Multiple Isomers
  

  Muhammad Khatib 

  Technion – Israel Institute of Technology, Israel

• 
  3:45 PM~4:20 PM

  T2-2 Integrated Molecule Recognition Sensor Electronics using Nanostrcured Metal Oxide on Silicon
  

  Takeshi Yanagida

  Kyushu University, Japan

• 
  4:20 PM~4:55 PM

  T2-3 Nanomechanical Sensors with AI towards Standard Olfactory IoT Sensing System
  

  Kosuke Minami

  NIMS, Japan

• 
  4:55 PM~5:30 PM

  T2-4 On the Detection, Characterization, and Identification of Single Molecule with Nanopores
  

  John J. Kasianowicz

  NIST, USA 

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Wednesday, April 18, 10:20 AM~12:05 PM

T5 ： Ferroelectrics on Si Technology

• 
  10:20 AM~10:55 AM

  T5-1 Hafnium oxide based ferroelectric devices for memories and beyond
  

  Stefan Slesazeck 

  NaMLab gGmbH, Germany 

• 
  10:55 AM~11:30 AM

  T5-2 Negative Capacitance Transistors
  

  Sayeef Salahuddin

  University of California, Berkeley, USA 

• 
  11:30 AM~12:05 PM

  T5-3 Device physics, design and challenge of Negative Capacitance FET
  

  Gengchiau Liang

  National University of Singapore, Singapore

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Wednesday, April 18, 3:30 PM~5:45 PM Ballroom A

T8 ： Future Patterning Solutions

• 
  3:30 PM~4:05 PM

  T8-1 Stochastic Limitations to EUV Lithography
  

  Chris A. Mack

  Fractilia, LLC, USA 

• 
  4:05 PM~4:40 PM

  T8-2 Novel Patterning schemes and technologies for the sub 5nm era
  

  Angélique Raley

  Tokyo Electron Ltd., USA 

• 
  4:40 PM~5:15 PM

  T8-3 Approaches and opportunities for area-selective atomic layer deposition
  

  Adrie Mackus

  Eindhoven University of Technology,  USA

• 
  5:15 PM~5:45 PM

  T8-4 Highly CMOS-compatible & Cost-efficient Patterning with Tilted-ion Implantation
  

  Sangwan Kim

  Ajou University, Korea 

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Thursday, April 19, 10:20 AM~12:40 PM Ballroom A

T9 ： Magnetic Materials & Memory

• 
  10:20 AM~10:55 AM

  T9-1 STT-MRAM for embedded memory applications from eNVM to Last Level Cache
  

  Po-Kang Wang

  Headway Technologies, USA 

• 
  10:55 AM~11:30 AM

  T9-2 Novel nanopatterning approach and improvements in STT-MRAM stacks for high density memory operation
  

  Bernard Dieny

  SPINTEC and CEA/Grenoble, France

• 
  11:30 AM~12:05 PM

  T9-3 Voltage-Control Spintronics Memory Having Potentials for High-Density and High-Speed Applications
  

  Hiroaki Yoda

  Toshiba Corporation, Japan 

• 
  12:05 PM~12:40 PM

  T9-4 The potential of nonvolatile magneto-electric devices for spintronic applications
  

  Peter Dowben

  University of Nebraska, USA 

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PAGE CONTENTS

• -J3 :
   Design and Technology Co-Optimization
• -J6 :
   Technology and Design Challenges for Next Generation Communication
• -T2 :
   Application of FET/Integration Technologies to Bio-sensing
• -T5 :
   Ferroelectrics on Si Technology
• -T8 :
   Future Patterning Solutions
• -T9 :
   Magnetic Materials & Memory