History of Best Student Paper Award

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Award Winners
2016 : Ming-Hsuan Kao, National Chiao Tung University, Taiwan
"A-SiGeC Thin Film Photovoltaic Enabled Self-Power Monolithic 3D IC Under Indoor Illumination"
Co-Authors: Chih-Chao Yang, Tsung-Ta Wu, Tung-Ying Hsieh, Wen-Hsien Huang, Hsing-Hsiang Wang, Chang-Hong Shen, Wen-Kuan Yeh, Meng-Fan Chang, and Jia-Min Shieh
Rong-Jhe Lyu, National Chiao Tung University, Taiwan
High-gain, Low-voltage BEOL Logic Gate Inverter Built with Film Profile Engineered IGZO Transistors

Yun-Hsuan Chiu, Horng-Chih Lin, Pei-Wen Li, and Tiao-Yuan Huang
2015 : Cheng-Ying Huang, University of California Santa Barbara, USA
"Ultrathin InAs-Channel MOSFETs on Si substrates"
Co-Authors: Xinyu Bao, Zhiyuan Ye, Sanghoon Lee, Hanwei Chiang, Haoran Li, Varistha Chobpattana, Brian Thibeault, William Mitchell, Susanne Stemmer, Arthur Gossard, Errol Sanchez, and Mark Rodwell
M. Edmonds, University of California San Diego , USA
"Passivation of surface defects on InGaAs (001) and (110) surfaces in preparation for subsequent gate oxide ALD"
T. J Kent, M. Chang, J.Kachian, R.Droopad, E. Chagarov, and A. C. Kummel

2014 :  Abhishek A. Sharma, Carnegie Mellon University, USA
"High-Speed In-situ Pulsed Thermometry in Oxide RRAMs"
Co-Authors: Mohammad Noman, Marek Skowronski, James A. Bain
Liang Zhao, Stanford University, USA
"Improved Multi-level Control of RRAM Using Pulse-Train Programming"
Co-Authors: Hong-Yu Chen, Shih-Chieh Wu, Zizhen Jiang, Shimeng Yu, Tuo-Hung Hou,
H.-S. Philip Wong, and Yoshio Nishi

:  Chun Wing Yeung, University of California, Berkeley, USA
"Low Power Negative Capacitance FETs for Future Quantum-Well Body Technology"
Co-Authors: Asif I. Khan, Asis Sarker, Sayeef Salahuddin, and Chenming Hu
Chunlei Zhan, National University of Singapore, Singapore
"(110)-Oriented Germanium-Tin (Ge0.97Sn0.03) P-channel MOSFETs"
Co-Authors: Wei Wang, Xiao Gong, Pengfei Guo, Bin Liu, Yue Yang, Genquan Han, and Yee-Chia Yeo 

:  Jing Wan, IMEP-LAHC, France
"Z2-FET: A zero-slope switching device with gate-controlled hysteresis"
Co-Authors: J. Wan, C. Le Royer, A. Zaslavsky, S. Cristoloveanu 
:  Shao-Ming Koh, National University of Singapore, Singapore
"New Tellurium Implant and Segregation for Contact Resistance Reduction and Single Metallic Silicide Technology for Independent Contact Resistance Optimization in n- and p-FinFETs"
Co-Authors: Eugene Yu Jin Kong, Bin Liu, Chee-Mang Ng, Pan Liu, Zhi-Qiang Mo, Kam-Chew Leong, Ganesh S. Samudra, and Yee-Chia Yeo

:  Jean-Luc Huguenin, ST Microelectronics / IMEP, France
Localized SOI Logic and Bulk I/O devices co-integration for Low Power System-on-Chip Technology”
Co-Authors: J.-L. Huguenin, S. Monfray, S. Denorme, G. Bidal, P. Perreau, S. Barnola, M.-P. Samson, K. Benotmane, N. Loubet, Y. Campidelli, F. Leverd, F. Abbate, L. Clement, C. Borowiak, Dominique Golanski, C. Fenouillet-Beranger, F. Boeuf, G. Ghibaudo, T. Skotnicki 

:  Dominique Fleury, STMicroelectronics/IMEP-LAHC laboratory, France
“A New Technique to Extract the Gate Bias Dependent S/D Series Resistance of Sub-100nm MOSFETs”
Co-Authors: Antoine Cros, Gregory Bidal, Hugues Brut, Emmanuel Josse and Gerard Ghibaudo

:  Eng-Huat Toh/Department of Electrical and Computer Engineering, National University of Singapore
“P-Channel I-MOS Transistor featuring Silicon Nano-Wire with Multiple-Gates, Si1-yCy I-region, in situ doped Si1-yCy Source, and Sub-5 mV/decade Subthreshold Swing”
Co-Authors: Grace Huiqi Wang, Doran Weeks, Ming Zhu, Trevan Landin, Jennifer Spear, Lap Chan, Shawn G. Thomas, Ganesh Samudra, and Yee-Chia Yeo

:  Donovan Lee/Electrical Engineering and Computer Sciences Department, University of California at Berkeley

“WetFET – A Novel Fluidic Gate-Dielectric Transistor for Sensor Application”
Co-Authors: Xin Sun, Emmanuel Quevy, Roger T. Howe, and Tsu-Jae King Liu
2006 :  Chia-Pin Lin / Dept. of Electronics Engineering & Inst.of Electronics, National Chiao Tung University
"Impact of Back Gate Bias on Hot-Carrier Effects of n-channel Tri-Gate FinFETs (TGFET)"
2005 :  Chung-Hsun Lin / Department of EECS, University of California at Berkeley
"Compact Modeling of FinFETs Featuring Independent-Gate Operation Mode"