Tuesday, April 17, 1:30 PM~2:50 PM Ballroom C
D1 Clocking Techniques

  • 1:30 PM~1:50 PM
    D1-1 A 25-Gb/s 13 mW Clock and Data Recovery Using C2MOS D-Flip-Flop in 65-nm CMOS
  • 1:50 PM~2:10 PM
    D1-2 Design of Divider Circuit for Electrochemical Impedance Spectroscopy Measurement System
  • 2:10 PM~2:30 PM
    D1-3 A ∆Σ DPLL with 1b TDC, 4b DTC and 8-Tap FIR Filter for Low-Voltage Clock Generation/Modulation Systems
  • 2:30 PM~2:50 PM
    D1-4 A CAPACITIVE CROSS-COUPLED GAN HEMT INJECTION-LOCKED FREQUENCY DIVIDER

Tuesday, April 17, 3:10 PM~4:10 PM Ballroom C
D2 Analog Interface Circuits

  • 3:10 PM~3:30 PM
    D2-1 A 473μW Wireless 16-Channel Neural Recording SoC with RF Energy Harvester
  • 3:30 PM~3:50 PM
    D2-2 A Cuffless Wearable System for Real-time Cutaneous Pressure Monitoring with Cloud Computing Assistance
  • 3:50 PM~4:10 PM
    D2-3 A 11-Bit 35-MS/s Wide Input Range SAR ADC in 180-nm CMOS Process

Tuesday, April 17, 4:50 PM~5:50 PM Ballroom C
D3 Circuits and Systems for Networking and Security

  • 4:50 PM~5:10 PM
    D3-1 High-Throughput Von Neumann Post-Processing for Random Number Generator
  • 5:10 PM~5:30 PM
    D3-2 High-Performance NTT Architecture for Large Integer Multiplication
  • 5:30 PM~5:50 PM
    D3-3 28nm Near/Sub-Threshold Dual-Port FIFO Memory for Shared Queues in Multi-Sensor Applications

Wednesday, April 18, 10:20 AM~11:20 AM Mezzanine A+B
D5 Power Management Techniques

  • 10:20 AM~10:40 AM
    D5-1 A High-Performance Current-Mode DC-DC Buck Converter with Adaptive Clock Control Technique
  • 10:40 AM~11:00 AM
    D5-2 A Digital Peak Current Delay Compensation for Primary-Side Regulation Flyback Adapter
  • 11:00 AM~11:20 AM
    D5-3 A 6.78MHz Active Voltage Doubler with Near-Optimal On/Off Delay Compensation for Wireless Power Transfer Systems

Wednesday, April 18, 11:30 AM~12:30 PM Mezzanine A+B
D6 Testing

  • 11:30 AM~11:50 AM
    D6-1 TSV-Aware 3D Test Wrapper Chain Optimization
  • 11:50 AM~12:10 PM
    D6-2 Hold Violation Analysis for Functional Test of Ultra-Low Temperature Circuits at Room Temperature
  • 12:10 PM~12:30 PM
    D6-3 Parallel Order ATPG for Test Compaction

Wednesday, April 18, 1:30 PM~2:50 PM Ballroom C
D7 Novel digital systems and emerging technology

  • 1:30 PM~1:50 PM
    D7-1 A 1.86mJ/Gb/Query Bit-Plane Payload Machine Learning Processor in 90nm CMOS
  • 1:50 PM~2:10 PM
    D7-2 Hardware Design of Disparity Computation for Stereo Vision Using Guided Image Filtering
  • 2:10 PM~2:30 PM
    D7-3 Using Approximate Circuits to Counter Process Imperfections in CNFET based Circuits
  • 2:30 PM~2:50 PM
    D7-4 The Application of Non-volatile Look-up-table Operations based on Multilevel-cell of Resistance Switching Random Access Memory

Wednesday, April 18, 3:10 PM~4:30 PM Ballroom C
D9 Advances in Physical Design and Verification

  • 3:10 PM~3:30 PM
    D9-1 A Learning-Based Methodology for Routability Prediction in Placement
  • 3:30 PM~3:50 PM
    D9-2 Triple Patterning Lithography-aware Detailed Routing Ensuring Via Layer Decomposability
  • 3:50 PM~4:10 PM
    D9-3 Diagnosis and Repair of Cells (DRC) Responsible for Power-Supply-Noise Violations
  • 4:10 PM~4:30 PM
    D9-4 MapReduce-Based Pattern Classification for Design Space Analysis

Wednesday, April 18, 4:50 PM~6:10 PM Ballroom C
D11 Emerging Techniques in EDA

  • 4:50 PM~5:10 PM
    D11-1 Using Range-equivalent Circuits for Facilitating Bounded Sequential Equivalence Checking
  • 5:10 PM~5:30 PM
    D11-2 Optimization of Threshold Logic Networks with ODC-based Node Merging
  • 5:30 PM~5:50 PM
    D11-3 An Ising Model Mapping to Solve Rectangle Packing Problem
  • 5:50 PM~6:10 PM
    D11-4 SOLAR: Simultaneous Optimization of Control-Layer Pins Placement and Channel Routing in Flow-Based Microfluidic Biochips

Thursday, April 19, 10:20 AM~11:20 AM Mezzanine A+B
D14 Energy Efficient Systems for Emerging Applications

  • 10:20 AM~10:40 AM
    D14-1 A High Learninig Capability Probabilistic Spiking Neural Network Chip
  • 10:40 AM~11:00 AM
    D14-2 DrowsyNet: Convolutional Neural Networks with Runtime Power-Accuracy Tunability Using Inference-Stage Dropout
  • 11:00 AM~11:20 AM
    D14-3 MORAS: An Energy-Scalable System using Adaptive Voltage Scaling

Thursday, April 19, 11:30 AM~12:30 PM Mezzanine A+B
D16 Architecture and Applications of Embedded Systems

  • 11:30 AM~11:50 AM
    D16-1 Double Asymmetric-latency Storage Class Memories (SCMs) for Fast-Write SCM, Fast-Read SCM & NAND Flash Hybrid SSDs
  • 11:50 AM~12:10 PM
    D16-2 A FAST ECG DIAGNOSIS BY USING SPECTRAL ARTIFICIAL NEURAL NETWORK (SANN) APPROACH
  • 12:10 PM~12:30 PM
    D16-3 Accurate and Fast Obstacle Detection Method for Automotive Applications Based on Stereo Vision

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