Tuesday, April 17, 1:30 PM~2:50 PM Ballroom C
D1 Clocking Techniques

  • 1:30 PM~1:50 PM
    D1-1 A 25-Gb/s 13 mW Clock and Data Recovery Using C2MOS D-Flip-Flop in 65-nm CMOS

    Ryosuke Noguchi, Kosuke Furuichi, Hiromu Uemura,
    Toshiyuki Inoue, Akira Tsuchiya and Keiji Kishine,Hiroaki Katsurai*, Shinsuke Nakano*and Hideyuki Nosaka**
    The University of Shiga Prefecture, 
    *NTT Device Innovation Center, NTT Corporation
    **NTT Device Technology Labs, NTT Corporation

  • 1:50 PM~2:10 PM
    D1-2 Design of Divider Circuit for Electrochemical Impedance Spectroscopy Measurement System
    Siang-Wei Wang, Tse-An Chen, Kuan-Hung Chen and Chia-Ling Wei, National Cheng Kung University
  • 2:10 PM~2:30 PM
    D1-3 A ∆Σ DPLL with 1b TDC, 4b DTC and 8-Tap FIR Filter for Low-Voltage Clock Generation/Modulation Systems
    Xiaohua Huang, Han Liu, Woogeun Rhee and Zhihua Wang, Tsinghua University
  • 2:30 PM~2:50 PM
    Sheng–Lyang Jang, Ke-Jen Lin, Wen-Cheng Lai and Miin-Horng Juang, National Taiwan University of Science and Technology

Tuesday, April 17, 3:10 PM~4:10 PM Ballroom C
D2 Analog Interface Circuits

  • 3:10 PM~3:30 PM
    D2-1 A 473μW Wireless 16-Channel Neural Recording SoC with RF Energy Harvester
    Kun-Ying Yeh, Yu-Jie Huang, Tung-Chien Chen, Liang-Gee Chen and  Shey-Shi Lu, National Taiwan University
  • 3:30 PM~3:50 PM
    D2-2 A Cuffless Wearable System for Real-time Cutaneous Pressure Monitoring with Cloud Computing Assistance
    Kun-Ying Yeh, Ting-Hao Lin, Yi-Yen Hsieh, Chia-Ming Chang, Yao-Joe Yang and Shey-Shi Lu, National Taiwan University
  • 3:50 PM~4:10 PM
    D2-3 A 11-Bit 35-MS/s Wide Input Range SAR ADC in 180-nm CMOS Process
    Wen-Chia Luo, Soon-Jyh Chang, Chun-Po Huang and Hao-Sheng Wu, National Cheng Kung University

Tuesday, April 17, 4:50 PM~5:50 PM Ballroom C
D3 Circuits and Systems for Networking and Security

  • 4:50 PM~5:10 PM
    D3-1 High-Throughput Von Neumann Post-Processing for Random Number Generator
    Ruilin Zhang, Sijia Chen, Chao Wan and Shinohara Hirofumi,
    Waseda University
  • 5:10 PM~5:30 PM
    D3-2 High-Performance NTT Architecture for Large Integer Multiplication
    Jheng-Hao Ye and Ming-Der Shieh, National Cheng Kung University
  • 5:30 PM~5:50 PM
    D3-3 28nm Near/Sub-Threshold Dual-Port FIFO Memory for Shared Queues in Multi-Sensor Applications

    Yi-Chun Wu*, Po-Tsang Huang*, Shun-Lin Wu*, Sheng-Chi Lung**, Wei-Chang Wang**, Wei Hwang* and Ching-Te Chuang*,
    *National Chiao Tung University
    **Faraday Technology Inc.

Wednesday, April 18, 10:20 AM~11:20 AM Mezzanine A+B
D5 Power Management Techniques

  • 10:20 AM~10:40 AM
    D5-1 A High-Performance Current-Mode DC-DC Buck Converter with Adaptive Clock Control Technique
    You-Te Chiu, Yu-Hsuan Liu, and Chung-Chih Hung, National Chiao Tung University
  • 10:40 AM~11:00 AM
    D5-2 A Digital Peak Current Delay Compensation for Primary-Side Regulation Flyback Adapter
    Chun-Ping Niou, Ta-Jin Chen and Chien-Hung Tsai,
    National Cheng Kung University
  • 11:00 AM~11:20 AM
    D5-3 A 6.78MHz Active Voltage Doubler with Near-Optimal On/Off Delay Compensation for Wireless Power Transfer Systems

    Fangyu Mao*^, Yan Lu*, Seng-Pan U*,** and Rui P.Martins*^,
    *University of Macau
    **Synopsis Ltd.
    ^Universidade de Lisboa 

Wednesday, April 18, 11:30 AM~12:30 PM Mezzanine A+B
D6 Testing

  • 11:30 AM~11:50 AM
    D6-1 TSV-Aware 3D Test Wrapper Chain Optimization
    Yu-Yi Wu and  Shih-Hsu Huang,
    Chung Yuan Christian University
  • 11:50 AM~12:10 PM
    D6-2 Hold Violation Analysis for Functional Test of Ultra-Low Temperature Circuits at Room Temperature
    Takahiro Nakayama and  Masanori Hashimoto,
    Osaka University
  • 12:10 PM~12:30 PM
    D6-3 Parallel Order ATPG for Test Compaction
    Yu-Wei Chen, Yu-Hao Ho, Chih-Ming Chang, Kai-Chieh Yang, Ming-Ting Li and James Chien-Mo Lee,
    National Taiwan University

Wednesday, April 18, 1:30 PM~2:50 PM Ballroom C
D7 Novel digital systems and emerging technology

  • 1:30 PM~1:50 PM
    D7-1 A 1.86mJ/Gb/Query Bit-Plane Payload Machine Learning Processor in 90nm CMOS

    Fang-Ju Ku*, Tung-Yu Wu**, Yen-Chin Liao*, Hsie-Chia Chang*, Wing-Hung Wong** and Chen-Yi Lee*,
    *National Chiao Tung University
    **Stanford University

  • 1:50 PM~2:10 PM
    D7-2 Hardware Design of Disparity Computation for Stereo Vision Using Guided Image Filtering

    Shen-Fu Hsiao* and Chih-Hsuan Chang**,
    *National Sun Yat-Sen University
    **MediaTek Inc.


  • 2:10 PM~2:30 PM
    D7-3 Using Approximate Circuits to Counter Process Imperfections in CNFET based Circuits
    Kaship Sheikh and Lan Wei,
    University of Waterloo
  • 2:30 PM~2:50 PM
    D7-4 The Application of Non-volatile Look-up-table Operations based on Multilevel-cell of Resistance Switching Random Access Memory

    Feng Zhang*, Dong-Yu Fan*,**, Qi-Peng Lin*, Qiang Huo*, Yun Li*, Lan Dai**, Cheng-Ying Chen^ and Hai-Hua Shen^^,
    *Institute of Microelectronics of Chinese Academy of Sciences
    **North China University of Technology
    ^Xiamen university of technology
    ^^University of Chinese Academy of Sciences

Wednesday, April 18, 3:10 PM~4:30 PM Ballroom C
D9 Advances in Physical Design and Verification

  • 3:10 PM~3:30 PM
    D9-1 A Learning-Based Methodology for Routability Prediction in Placement
    Li-Chin Chen, Chien-Chia Huang, Yao-Ling Chang and Hung-Ming Chen,
    National Chiao Tung University 
  • 3:30 PM~3:50 PM
    D9-2 Triple Patterning Lithography-aware Detailed Routing Ensuring Via Layer Decomposability
    Hua-Yi Wu and Shao-Yun Fang,
    National Taiwan University of Science and Technology
  • 3:50 PM~4:10 PM
    D9-3 Diagnosis and Repair of Cells (DRC) Responsible for Power-Supply-Noise Violations
    Yu-Ching Li, Shih-Yao Lin, Heng-Yi Lin, and James Chien-Mo Li, National Taiwan University
  • 4:10 PM~4:30 PM
    D9-4 MapReduce-Based Pattern Classification for Design Space Analysis

    Yan-Shiun Wu*, Hong-Yan Su*, Yi-Hsiang Chang**, Rasit Onur Topaloglu^ and Yih-Lang Li*,
    *National Chiao Tung University
    **National Tsing Hua University


Wednesday, April 18, 4:50 PM~6:10 PM Ballroom C
D11 Emerging Techniques in EDA

  • 4:50 PM~5:10 PM
    D11-1 Using Range-equivalent Circuits for Facilitating Bounded Sequential Equivalence Checking
    Yung-Chih Chen*, Wei-An Ji**, Chih-Chung Wang**, Ching-Yi Huang**, Chia-Cheng Wu**, Chia-Chun Lin** and Chun-Yao Wang**,
    *Yuan Ze University
    **National Tsing Hua University
  • 5:10 PM~5:30 PM
    D11-2 Optimization of Threshold Logic Networks with ODC-based Node Merging
    Fu-Lian Wong, Li-Cheng Zheng and Yung-Chih Chen,
    Yuan Ze University
  • 5:30 PM~5:50 PM
    D11-3 An Ising Model Mapping to Solve Rectangle Packing Problem
    Kotaro Terada*, Daisuke Oku*, Sho Kanamaru*, Shu Tanaka*,**, Masato Hayashi^, Masanao Yamaoka^, Masao Yanagisawa* and Nozomu Togawa*,
    *Waseda University
    **Precursory Research for Embryonic Science and Technology
    ^Hitachi, Ltd.
  • 5:50 PM~6:10 PM
    D11-4 SOLAR: Simultaneous Optimization of Control-Layer Pins Placement and Channel Routing in Flow-Based Microfluidic Biochips
    Jia-Lin Wu*, Katherine Shu-Min Li**, Jain-De Li**, Sying-Jyan Wang** and Tsung-Yi Ho^,
    *National Sun Yat-Sen University
    **National Chung Hsing University
    ^National Tsing Hua University

Thursday, April 19, 10:20 AM~11:20 AM Mezzanine A+B
D14 Energy Efficient Systems for Emerging Applications

  • 10:20 AM~10:40 AM
    D14-1 A High Learninig Capability Probabilistic Spiking Neural Network Chip
    Hung-Yi Hsieh, Pin-Yi Li, Cheng-Han Yang and Kea-Tiong Tang,
    National Tsing Hua University
  • 10:40 AM~11:00 AM
    D14-2 DrowsyNet: Convolutional Neural Networks with Runtime Power-Accuracy Tunability Using Inference-Stage Dropout
    Ren-Shuo Liu, Yun-Chen Lo, Yuan-Chun Luo, Chih-Yu Shen and  Cheng-Ju Lee,
    National Tsing Hua University
  • 11:00 AM~11:20 AM
    D14-3 MORAS: An Energy-Scalable System using Adaptive Voltage Scaling
    Kuo-Chiang Chang, Shien-Chun Luo, Ching-Ji Huang, Jia-Hung Peng, and Yuan-Hua Chu,
    Industrial Technology Research Institute

Thursday, April 19, 11:30 AM~12:30 PM Mezzanine A+B
D16 Architecture and Applications of Embedded Systems

  • 11:30 AM~11:50 AM
    D16-1 Double Asymmetric-latency Storage Class Memories (SCMs) for Fast-Write SCM, Fast-Read SCM & NAND Flash Hybrid SSDs
    Yutaka Adachi, Chihiro Matsui and Ken Takeuchi, Chuo University
  • 11:50 AM~12:10 PM

    Kun-Chih (Jimmy) Chen and Po-Cheng Chien, National Sun Yat-Sen University

  • 12:10 PM~12:30 PM
    D16-3 Accurate and Fast Obstacle Detection Method for Automotive Applications Based on Stereo Vision
    Yi-Chin Tsai, Jih-Hsiang Cheng, Yun Chen and Kuan-Hung Chen,
    FengChia University