Tuesday, April 25, 11:50 AM~12:20 PM Ballroom D

T1 ： Poster Session

• T1-1 Analytical Solution for RESURF and Breakdown Characteristics of Finger STI DEMOS Transistors
  

  H.C. Tsai*, R.H. Liou, and C.H. Lien*

  Taiwan Semiconductor Manufacturing Company, Taiwan

  *National Tsing Hua University, Taiwan 

• T1-2 Impacts of Work Function Variation and Line Edge Roughness on Hybrid TFET-MOSFET Monolithic 3D SRAMs
  

  Jian-Hao Wang, Pin Su, and Ching-Te Chuang

  National Chiao Tung University, Taiwan

• T1-3 Evaluation of Analog Performance of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) MOSFETs
  

  Hung-Yi Lee, Chang-Hung Yu, Pin Su, and Ching-Te Chuang

  National Chiao Tung University, Taiwan  

• T1-4 Performance Evaluation of Pass-Transistor-Based Circuits using Monolayer and Bilayer 2-D Transition Metal Dichalcogenide (TMD) MOSFETs for 5.9nm Node
  

  Chang-Hung Yu, Jun-Teng Zheng, Pin Su, and Ching-Te Chuang

  National Chiao Tung University, Taiwan

• T1-5 Twin Gate Tunnel FET based Capacitorless Dynamic Memory
  

  Nupur Navlakha, Jyi-Tsong Lin*, and Abhinav Kranti

  Indian Institute of Technology Indore, India

  *National Sun Yat-Sen University, Taiwan

• T1-6 Ge n-channel FinFET Performance Enhancement Using Low Work Function Metal-Interfacial Layer-Ge Contacts
  

  Prashanth P. Manik, Sachin Dev, Nayana Remesh, Yaksh Rawal, Siddhant Khopkar, and Saurabh Lodha

  Indian Institute of technology Bombay, India 

• T1-7 Investigation and Comparison of Design Space for Ultra-Thin-Body GeOI/SOI Negative Capacitance FETs
  

  Ho-Pei Lee, Chien-Lin Yu, Wei-Xiang You, and Pin Su

  National Chiao Tung University, Taiwan

• T1-8 Temperature Compensated Super-High-Frequency (2-8 GHz) Surface Acoustic Wave Devices
  

  Salahuddin Raju, Changjian Zhou*, Bin Li*, and Mansun Chan

  Hong Kong University of Science and Technology, Hong Kong

  *South China University of Technology, China

• T1-9 Impact of Substrate on the Frequency Behavior of Trans-conductance in Ultra-thin Body and BOX FDSOI MOS Devices – A Physical Insight
  

  Mandar Bhoir, Pragya Kushwaha*, Yogesh S. Chauhan**, and Nihar R. Mohapatra

  Indian Institute of Technology Gandhinagar, India

  *University of California, Berkeley, USA

  **Indian Institute of Technology Kanpur, India

• T1-10 TCAD-Based Characterization of Logic Cells: Power, Performance, Area, and Variability
  

  HW. Karner, C. Kernstock, Z. Stanojevic, O. Baumgartner, F. Schanovsky, *D. Helms, *R. Eilers, *M. Metzdorf, and M. Karner

  Global TCAD Solutions, Austria

  *OFFIS, Germany 

• T1-11 Scaling of Gate Dielectric on Ge Substrate (Late News Paper)
  

  Yung-Hsiang Chan and Bing-Yue Tsui

  National Chiao Tung University, Taiwan

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Wednesday, April 26, 10:20 AM~11:40 AM Ballroom A

T4 ： RRAM

• T4-1 Filament Control of Field-Enhanced WOx Resistive Memory Toward Low Power Applications
  

  Chao-Hung Wang, Kuang-Hao Chiang, Yu-Hsuan Lin, Jau-Yi Wu, Yung-Han Ho, Erh-Kun Lai, Dai-Ying Lee, Ming-Hsiu Lee, Kuang-Yeu Hsieh, and Chih-Yuan Lu

  Macronix International Co., Ltd., Taiwan

• T4-2 Occurrence and Solution to Overcome 1st RESET Resistance Pinning Effect in Ti/HfOx based RRAM for Low Power Nonvolatile Memory Applications
  

  Sk. Ziaur Rahaman, Heng-Yuan Lee, Yu-De Lin, Chien-Hua Hsu, Kan-Hsueh Tsai, Wei-Su Chen, Yu-Sheng Chen, Pang-Shiu Chen*, and Pei-Hua Wang

  Industrial Technology Research Institute, Taiwan

  *MingShin University of Science and Technology, Taiwan

• T4-3 A High Accuracy and Robust Machine Learning Network for Pattern Recognition Based on Binary RRAM devices
  

  Chen Liu, Runze Han, Sheng Zhang, Maochuan Li, Zheng Zhou, Peng Huang, Lifeng Liu, Xiaoyan Liu, and Jinfeng Kang

  Peking University, China  

• T4-4 Design and Optimization of Strong Physical Unclonable Function (PUF) Based on RRAM Array
  

  Yachuan Pang, Huaqiang Wu, Bin Gao, Rui Liu*, Shan Wang, Shimeng Yu*, An Chen**, and He Qian

  Tsinghua University, China

  *Arizona State University, USA

  **Semiconductor Research Corporation, USA 

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Wednesday, April 26, 10:20 AM~11:40 AM Ballroom B

T5 ： Interface and 3D Integration

• T5-1 A Universal Model for Interface-type Threshold Switching Phenomena by Comprehensive Study of Vanadium Oxide-Based Selector
  

  Chih-Yang Lin, Ying-Chen Chen*, Meiqi Guo*,****, Chih-Hung Pan, Fu-Yuan Jin, Yi-Ting Tseng, Cheng Chih Hsieh*, Xiaohan Wu*, Min-Chen Chen, Yao-Feng Chang**, Fei Zhou***, Burt Fowler*, Kuan-Chang Chang, Tsung-Ming Tsai, Ting-Chang Chang, Yonggang Zhao, Simon M. Sze*****, Sanjay Banerjee*, and Jack C. Lee*

  National Sun Yat-Sen University, Taiwan

  *The University of Texas at Austin, USA

  **Micron Technology Inc., USA

  ***SanDisk, USA

  ****Tsinghua University, China

  *****National Chiao Tung University, Taiwan

• T5-2 On the Physical Modeling of Random Telegraph Noise (RTN) Amplitude in Nanoscale MOSFETs: From Ideal to Statistical Devices
  

  Zexuan Zhang, Shaofeng Guo, Zhe Zhang, Runsheng Wang, and Ru Huang

  Peking University, China  

• T5-3 A Design Methodology of Efficient On-Chip Wireless Power Transmission
  

  Salahuddin Raju, Clarissa C. Prawoto, Mansun Chan, and C. Patrick Yue

  Hong Kong University of Science and Technology, Hong Kong 

• T5-4 Development and Electrical Investigation of Through Glass Via and Through Si Via in 3D Integration
  

  Geng-Ming Chang, Shih-Wei Lee, Ching-Yun Chang, and Kuan-Neng Chen

  National Chiao Tung University, Taiwan  

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Wednesday, April 26, 1:30 PM~3:10 PM Ballroom A

T6 ： Novel Device

• T6-1 Contact Engineering and Channel Doping for Robust Carbon Nanotube NFETs
  

  Jianshi Tang*, Damon B. Farmer*, Sarunya Bangsaruntip*, Kuan-Chang Chiu*,**, Bharat Kumar*, and Shu-Jen Han*

  *IBM Thomas J. Watson Research Center, USA 

  **National Tsing Hua University, Taiwan

• T6-2 Asymmetric S/D Contacts with BN Tunneling Barrier on Black Phosphorous FETs
  

  Lingming Yang, Mengwei Si, Qing Paduano*, Mike Snure*, and Peide Ye

  Purdue University, USA

  *Air Force Research Laboratory, USA

• T6-3 Density Functional Theory Molecular Dynamics Simulations and Experimental Measurements of a-HfO2/a-SiO/SiGe(001) and a-HfO2/a-SiO2/SiGe(001) interfaces
  

  E. Chagarov, K. Sardashti, I. Kwak, S. Ueda , M. Yakimov*, S. Oktyabrsky*, and A. C. Kummel

  University of California San Diego, USA

  *SUNY Polytechnic Institute, USA

• T6-4 A Steep Slope Phase-FET based on 2D MoS2 and the Electronic Phase Transition in VO2
  

  Benjamin Grisafe, Nikhil Shukla, Matthew Jerry, and Suman Datta

  University of Notre Dame, USA  

• T6-5 Ion Implantation after Germanidation technique for Low Thermal Budget Ge CMOS devices: from Bulk Ge to UTB-GeOI substrate
  

  Wen Hsin Chang, Toshifumi Irisawa, Hiroyuki Ishii, Hiroyuki Hattori, Hiroyuki Ota, Noriyuki Uchida, and Tatsuro Maeda

  National Institute of Advanced Industrial Science and Technology, Japan 

• T6-6 Selective Etching of Silicon in Preference to Germanium and Si0.5Ge0.5 (Late News Paper)
  

  Christopher F. Ahles, Jong Youn Choi, Steven Wolf, and Andrew C. Kummel

  University of California San Diego, USA

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Wednesday, April 26, 3:30 PM~4:50 PM Ballroom A

T7 ： Transistor

• T7-1 I/O Device Optimization Techniques Tailored for Highly-scaled FinFET Technology
  

  Ming-Huei Lin, Chung-An Hu, Chia-Cheng Chen, Tien-Shun Chang, Yun-Ju Sun, Hou-Yu Chen, Vincent S. Chang, and Shyh-Horng Yang

  Taiwan Semiconductor Manufacturing Company, Taiwan 

• T7-2 Stressor Design for FinFETs with Air-Gap Spacers
  

  Darsen D. Lu, Angada B. Sachid*, Yao-Min Huang**, Yi-Ju Chen**, Chun-Chi Chen**, Min-Cheng Chen**, and Chenming Hu*

  National Cheng Kung University, Taiwan 

  *University of California, Berkeley, USA

  **National Nano Device Laboratories, Taiwan

• T7-3 Semiconductor-On-Insulator Lateral Bipolar Transistors for High-Speed Low-Power Applications
  

  Jeng-Bang Yau, J. Cai, T. H. Ning, and K. K. Chan

  IBM Thomas J. Watson Research Center, USA  

• T7-4 A Novel Design of P-N Staggered Face-tunneling TFET Targeting for Low Power and Appropriate Performance Applications
  

  E. R. Hsieh, Y. C. Fan*, K. Y. Chang*, C. H. Liu*, C. H. Chien, and Steve S. Chung

  National Chiao Tung University, Taiwan

  *National Taiwan Normal University, Taiwan

• T7-5 Ferroelectricity in HfO2 thin films as a function of Zr doping (Late News Paper)
  

  Golnaz Karbasian, Ava Tan, Ajay Yadav, Eric Martin Henry Sorensen, Claudy Rayan Serrao, Asif Islam Khan, Korok Chatterjee, Sangwan Kim, Chenming Hu, and Sayeef Salahuddin

  University of California, Berkeley, USA

• 
  T7-6 Integration of III-V Nanowires for the next RF- and logic technology generation (Invited Talk)
  

  Lars-Erik Wernersson 

  Lund University, Sweden

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Thursday, April 27, 10:20 AM~12:00 PM Ballroom B

T9 ： Memory

• T9-1 Exploration and Evaluation of TCAM with Hybrid Tunneling FET and FinFET Devices for Ultra-Low-Voltage Applications
  

  Meng-Hsuan Tu, Yin-Nien Chen, Pin Su, and Ching-Te Chuang

  National Chiao Tung University, Taiwan  

• T9-2 Dense N over CMOS 6T SRAM Cells using 3D Sequential Integration
  

  C-M. V. Lu*,**, C. Fenouillet-Beranger*, M. Brocard*, O. Billoint*, G. Cibrario*, L. Brunet*, X. Garros*, C. Leroux*, M. Casse*, A. Laurent*, A. Toffoli*, G. Romano*,**, R. Kies*, R. Gassilloud*, N. Rambal*, V. Lapras*, M-P. Samson*,**, C. Tallaron*,**, C. Tabone*, B. Previtali*, D. Barge**, A. Ayres*,**, L. Pasini*,**, P. Besombes*, F. Andrieu*, P. Batude*, T. Skotnicki**, and M. Vinet*

  *CEA-Leti, France

  **STMicroelectronics, France 

• T9-3 An Investigation of Program Disturb Characteristics and Data Pattern Effect in 128G 3D NAND Flash Memories
  

  Yu-Hung Yeh, Sheng-Hung Shih, Jen-Chien Fu*, Chrong-Jung Lin, and Ya-Chin King

  National Tsing Hua University, Taiwan

  *Lite-On Technology Corp., Taiwan 

• T9-4 Hardware Implementation of Physically Unclonable Function (PUF) in Perpendicular STT MRAM
  

  D. Y. Wang, Y. C. Hsin, K. Y. Lee, G. L. Chen, S. Y. Yang, H. H. Lee, Y. J. Chang, I. J. Wang, Y. C. Kuo, Y. S. Chen, P. H. Wang, C. I. Wu, and D. D. Tang

  Industrial Technology Research Institute, Taiwan  

• T9-5 A Magnetic Shift Register with Periodic Potential Energy Modulation
  

  T. Kondo, H. Morise, T. Shimada, M. Quinsat, M. Kado, Y. Ootera, and S. Nakamura

  Toshiba Corporation, Japan 

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PAGE CONTENTS

• -T1 :
   Poster Session
• -T4 :
   RRAM
• -T5 :
   Interface and 3D Integration
• -T6 :
   Novel Device
• -T7 :
   Transistor
• -T9 :
   Memory