Contact
Welcome
General Info
Scope
Venue
Awards
Future Conference
Previous Conferences
Committees
2017 Committees
Authors
Regular Paper Submission
Late News Paper Submission
Program
Schedule
Short Courses
Joint Plenary Sessions
Joint Luncheon Keynote
Special Sessions
Regular Sessions
Cocktail Reception
Attendees
Online Registration
Onsite Registration Center
Hotel Information
Visa for arriving Taiwan
Sponsorship
Registration
Tuesday, April 25, 1:30 PM~5:20 PM Ballroom B
J2
:
Joint Special Session: Foundry Eco-system
J2-1
TCAD Based Design-Technology Co-Optimisations in advanced technology nodes
J2-3
Industrial performance to serve economical rebound
J2-4
Building best in class System solutions : Enabled by collaboration
J2-5
Collaboration and Innovation for Your Success
J2-6
Navigating through the fragmented application maze
J2-7
RRAM Technology and Its Embedded Potential on IoT Applications
1:30 PM~5:20 PM
J2-2
New Embedded Memories, from Lab to Fab
Wednesday, April 26, 1:30 PM~5:20 PM Ballroom B
J5
:
Joint Special Session: Embedded Memory System
J5-2
Low-Current Spin Transfer Torque MRAM
J5-3
Embedded Nonvolatile Memory with STT-MRAMs and its Application for Nonvolatile Brain-Inspired VLSIs
J5-4
Embedded non-volatile memory design from cell to system levels
J5-5
STT-MRAM memories for IoT applications: challenges and opportunities at circuit level and above
J5-6
Utilizing NVDIMM to alleviate the I/O Performance Gap for Big Data Workloads
1:30 PM~2:05 PM
J5-1
Novel memory hierarchy with e-STT-MRAM for near-future applications
Tuesday, April 25, 1:30 PM~3:15 PM Ballroom A
T2
:
Special Session: Future of Lithography
T2-1
EUV extendibility research at Berkeley Lab
T2-2
DSA : Progress Toward Industry Acceptance
T2-3
Electron Multi-Beam Technology
Tuesday, April 25, 3:35 PM~5:55 PM Ballroom A
T3
:
Special Session: Emerging Research Device
T3-1
Negative Capacitance FETs with Steep Switching by Ferroelectric Hf-based Oxide
T3-2
III-V/Ge MOSFETs and TFETs for Ultra-Low Power Logic LSIs
T3-3
High Performance PMOS with Strained High-Ge-Content SiGe Fins for Advanced Logic Applications
T3-4
InGaAs Quantum-Well MOSFETs for future logic applications
Thursday, April 27, 10:20 AM~12:40 PM Ballroom A
T8
:
Special Session: 2016 Technology Highlights
T8-1
Device-Architecture Co-Design for Hyperdimensional Computing with 3D Vertical Resistive Switching Random Access Memory (3D VRRAM)
T8-2
1x- to 2x-nm MTJ switching at sub-3 ns pulses with compatible current in sub-20 nm CMOS for high performance embedded STT-MRAM
T8-3
Back-Side Integration of Hybrid III-V on Silicon DBR Lasers
T8-4
Novel TFET Circuits for High-Performance Energy-Efficient Heterogeneous MOSFET/TFET Logic
PAGE CONTENTS
-
J2 :
Joint Special Session: Foundry Eco-system
-
J5 :
Joint Special Session: Embedded Memory System
-
T2 :
Special Session: Future of Lithography
-
T3 :
Special Session: Emerging Research Device
-
T8 :
Special Session: 2016 Technology Highlights
Top
×
Close