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Tuesday, April 25, 1:30 PM~2:50 PM Ballroom C
D1 ： Intelligent Digital System

  • 1:30 PM~1:50 PM
    D1-1 Low-Latency Voltage-Racing Winner-Take-All (VR-WTA) Circuit for Acceleration of Learning Engine
    Chai-Heng Wu,Ting-Sheng Chen, Ding-Yuan Lee, Tsung-Te Liu, and An-Yeu Wu
    National Taiwan University, Taiwan
  • 1:50 PM~2:10 PM
    D1-2 Hybrid Spiking-Stochastic Deep Neural Network
    Heesu Kim, Joonsang Yu, and Kiyoung Choi
    Seoul National University, Korea
  • 2:10 PM~2:30 PM
    D1-3 Design and Implementation of a 3D Hand Gesture Architecture System Under Complicated Environment
    Tsung-Han Tsai and Yih-Ru Tsai
    National Central University, Taiwan
  • 2:30 PM~2:50 PM
    D1-4 High-Speed and Low-Power VLSI-Architecture for Inexact Speculative Adder
    Rahul Shrestha
    Indian Institute of Technology (IIT) Mandi, India

Tuesday, April 25, 3:10 PM~4:30 PM Ballroom C
D2 ： Analog Techniques

  • 3:10 PM~3:30 PM
    D2-1 A Solar-Powered Single-Inductor Dual-Output (SIDO) DC-DC Boost for Power Management Unit System with High Light-Load Efficiency
    Lee Chuang, Chun-Chang Wu, Wei-Heng Wang, and Shey-Shi Lu
    National Taiwan University, Taiwan
  • 3:30 PM~3:50 PM
    D2-2 A Digitally Controlled Buck Converter with Current Sensor-less Adaptive Voltage Positioning (AVP) Mechanism
    Kai-Yu Hu, Bo-Ming Chen, and Chien-Hung Tsai
    National Cheng Kung University, Taiwan
  • 3:50 PM~4:10 PM
    D2-3 A 45 μW, 9.5 MHz Current-Reused RC Oscillator Using a Swing-Boosting Technique
    Shao-Yung Lu and Yu-Te Liao
    National Chiao Tung University, Taiwan
  • 4:10 PM~4:30 PM
    D2-4 A Current Feedback Instrumentation Amplifier with Chopping and Dynamic Element Matching Techniques and Employing the Current-Reuse Technique in Input/Feedback Stages
    Tzu-Ying Chen, Yi-Ling Tsai, and Tsung-Hsien Lin
    National Taiwan University, Taiwan

Tuesday, April 25, 4:50 PM~6:10 PM Ballroom C
D3 ： Emerging Platform and Applications for Embedded Systems

  • 4:50 PM~5:10 PM
    D3-1 A Hadoop-based Principle Component Analysis on Embedded Heterogeneous Platform
    Sheng-Yen Chen1, Chia-I Wei2, Yu-Chen Chiu1, and Bo-Cheng Lai1
    1National Chiao Tung University, Taiwan
    2University of California, San Diego
  • 5:10 PM~5:30 PM
    D3-2 A Body Sensor Node SoC for ECG/EMG Applications with Compressed Sensing and Wireless Powering
    Yo-Hao Tu, Kai-Wen Yao, Ming-Hao Huang, Yu-Yun Lin, Hao-Yu Chi, Po-Min Cheng, Pei-Yun Tsai, Muh-Tian Shiue, Chien-Nan Liu, Kuo-Hsing Cheng, and Jia-Shiang Fu
    National Central University, Taiwan
  • 5:30 PM~5:50 PM
    D3-3 An Adaptive Cross-window Stereo Camera Distance Estimation Technology and its System Implementation for Multiple Applications
    Ricky Lee, Tai-En Wu, and Jiun-In Guo
    National Chiao Tung University, Taiwan
  • 5:50 PM~6:10 PM
    D3-4 A Vision Radar System for Car Safety Driving Applications
    Chia-Chi Tsai, Yi-Ting Lai, Yuan-Fu Li, and Jiun-In Guo
    National Chiao Tung University, Taiwan

Wednesday, April 26, 10:20 AM~11:20 AM Ballroom D
D5 ： Memory and Interconnection for SoC

  • 10:20 AM~10:40 AM
    D5-1 Design Space Exploration with a Cycle-accurate SystemC/TLM DRAM Controller Model
    Ting-Shuo Hsu, Chao-Chih Wu, Che-Wei Hsu, Chih-Tsun Huang, Jing-Jia Liou, Yao-Hua Chen, and Juin-Ming Lu
    National Tsing Hua University, Taiwan
  • 10:40 AM~11:00 AM
    D5-2 Reducing Aging on Scratchpad Memory Using Temporal- and FSM-based Power Management
    Yun-Kae Law, Cheng-Chien Lin, and Ing-Chao Lin
    National Cheng Kung University, Taiwan
  • 11:00 AM~11:20 AM
    D5-3 Optimization for Application-Specific Packet-Based On-Chip Interconnects Using a Cycle-Accurate Model
    Yu-Ju Shih, Chih-Tsun Huang, Jing-Jia Liou, Jyu-Yuan Lai, Chih-Wea Wang, and Chi-Feng Wu 
    National Tsing Hua University, Taiwan 

Wednesday, April 26, 11:30 AM~12:30 PM Ballroom D
D6 ： Thermal- and Variation-Aware Optimization for System Designs

  • 11:30 AM~11:50 AM
    D6-1 A Low Power Synthesis Flow for Multi-Rate Systems
    Hsin-Pang Kuo, Alan P. Su, and Kuen-Jong Lee
    National Cheng Kung University, Taiwan
  • 11:50 AM~12:10 PM
    D6-2 Utilization of Relieved Corners from Multi-corner Libraries in Deterministic Static Timing Analysis
    Hyun-jeong Kwon and Young-Hwan Kim
    POSTECH, Korea
  • 12:10 PM~12:30 PM
    D6-3 Thermal Sensor Allocation and Full-System Temperature Characterization for Thermal-aware Mesh-based NoC System by Using Compressive Sensing Technique
    Kun-Chih Chen, Yu-Hsien Chen, ana Yen-Po Lin
    National Sun Yat-Sen University, Taiwan

Wednesday, April 26, 1:30 PM~2:30 PM Ballroom C
D7 ： Wireless Transceiver

  • 1:30 PM~1:50 PM
    D7-1 A Four-band TD-LTE Transmitter with Wide Dynamic Range and LPF Bandwidth Calibration
    Zhen Liang, Bin Li, Mo Huang, Hui Ye, Ken Xu, Yutao Liu, and Yan Lu
    South China University of Technology, China
  • 1:50 PM~2:10 PM
    D7-2 A Digital IQ Imbalance Self-Calibration in FDD Transceiver
    Hui Ye, Bin Li, Mo Huang, Zhen Liang, and Yan Lu
    South China University of Technology, China
  • 2:10 PM~2:30 PM
    D7-3 A 0.9-V 2.36-GHz MedRadio-Band 10-Mbps Low-Power OOK Modulator for Neural Implants
    Chien-Hua Jung and Kea-Tiong Tang
    National Tsing Hua University, Taiwan

Wednesday, April 26, 3:10 PM~4:30 PM Ballroom C
D9 ： Advanced Digital Systems

  • 3:10 PM~3:30 PM
    D9-1 A 6.4G LLR/s 8x8 64-QAM Soft-Output MIMO Detector with Lattice Reduction Preprocessing
    Jing-You Lin, Jung-Chun Chi, Chun-Fu Liao, and Yuan-Hao Huang
    National Tsing Hua University, Taiwan
  • 3:30 PM~3:50 PM
    D9-2 A Reference-Less All-Digital Transceiver for Human Body Channel Communication
    Ching-Che Chung, Yi-Che Tsai, and Ming-Chieh Li
    National Chung Cheng University, Taiwan
  • 3:50 PM~4:10 PM
    D9-3 WIDE-I/O 3D-STAKED DRAM CONTROLLER FOR NEAR-DATA PROCESSING SYSTEM
    Yu-Hsuan Lin, Shih-Fan Peng, and Wei Hwang
    Nation Chiao Tung University, Taiwan
  • 4:10 PM~4:30 PM
    D9-4 Analysis and Reduction of SRAM PUF Bit Error Rate
    Hirofumi Shinohara, Baikun Zheng,Yanhao Piao, Bo Liu, and Shiyu Liu
    Waseda University, Japan

Wednesday, April 26, 4:50 PM~6:10 PM Ballroom C
D11 ： Test and Reliability for Advanced Process Technologies

  • 4:50 PM~5:10 PM
    D11-1 Robust Test Pattern Generation for Hold-time Faults in Nanometer Technologies
    Yu-Hao Ho, Yo-Wei Chen, Chih-Ming Chang, Kai-Chieh Yang, and Chien-Mo Li
    National Taiwan University, Taiwan
  • 5:10 PM~5:30 PM
    D11-2 On Designing Two-Dimensional Scan Architecture for Test Chips
    Yu Huang and Wu-Tung Cheng
    Mentor Graphics, USA
  • 5:30 PM~5:50 PM
    D11-3 On-Chip Temperature and Process Variation Sensing using a Reconfigurable Ring Oscillator
    Tadashi Kishimoto, Tohru Ishihara, and Hidetoshi Onodera
    Kyoto University, Japan

Thursday, April 27, 10:20 AM~11:20 AM Mezzanine A+B
D14 ： Advances in Placement and Routing

  • 10:20 AM~10:40 AM
    D14-1 Detailed Routing Violation Prediction During Placement Using Machine Learning
    Aysa Fakheri Tabrizi, Nima Karimpour Darav, Logan Rakai, Andrew Kennings, and Laleh Behjat
    University of Calgary, Canada
  • 10:40 AM~11:00 AM
    D14-2 Layout Placement Optimization with Isolation Rings for High-Voltage VLSI Circuits
    Chih-Wei Lee, Hwa-Yi Tseng, Chi-Lien Kuo, Chien-Nan Liu, and Chin Hsia
    National Central University, Taiwan
  • 11:00 AM~11:20 AM
    D14-3 An Analytical Placer for Heterogeneous FPGAs via Rough-Placed Packing
    Wan-Ning Wu, Chen Chen, Ching-Yu Chin, Chun-Kai Wang, and Hung-Ming Chen
    National Chiao Tung University, Taiwan

Thursday, April 27, 11:30 AM~12:30 PM Mezzanine A+B
D15 ： ADC and PLL

  • 11:30 AM~11:50 AM
    D15-1 An 8-bit 400-MS/s Calibration-Free SAR ADC with a Pre-amplifier-only Comparator
    Chih-Huei Hou, Soon-Jyh Chang, Hao-Sheng Wu, Huan-Jui Hu, and En-Ze Cun
    National Cheng Kung University, Taiwan
  • 11:50 AM~12:10 PM
    D15-2 A 10-bit 100-MS/s SAR ADC With Capacitor Swapping Technique in 90-nm CMOS
    Yung-Hui Chung and Song-You Shih
    National Taiwan University of Science and Technology, Taiwan
  • 12:10 PM~12:30 PM
    D15-3 An All-Digital Phase-Locked Loop with a Multi-Delay-Switching TDC
    Zhong-Cheng Su and Chung-Chih Hung
    National Chiao Tung University, Taiwan

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