D1 ： Intelligent Digital System

1:30 PM~2:50 PM,Tuesday , April 25 Ballroom C

• D1-1 Low-Latency Voltage-Racing Winner-Take-All (VR-WTA) Circuit for Acceleration of Learning Engine
  

  1:30 PM~1:50 PM,Tuesday , April 25

  Chai-Heng Wu,Ting-Sheng Chen, Ding-Yuan Lee, Tsung-Te Liu, and An-Yeu Wu

  National Taiwan University, Taiwan

• D1-2 Hybrid Spiking-Stochastic Deep Neural Network
  

  1:50 PM~2:10 PM,Tuesday , April 25

  Heesu Kim, Joonsang Yu, and Kiyoung Choi

  Seoul National University, Korea

• D1-3 Design and Implementation of a 3D Hand Gesture Architecture System Under Complicated Environment
  

  2:10 PM~2:30 PM,Tuesday , April 25

  Tsung-Han Tsai and Yih-Ru Tsai

  National Central University, Taiwan

• D1-4 High-Speed and Low-Power VLSI-Architecture for Inexact Speculative Adder
  

  2:30 PM~2:50 PM,Tuesday , April 25

  Rahul Shrestha

  Indian Institute of Technology (IIT) Mandi, India

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D2 ： Analog Techniques

3:10 PM~4:30 PM,Tuesday , April 25 Ballroom C

• D2-1 A Solar-Powered Single-Inductor Dual-Output (SIDO) DC-DC Boost for Power Management Unit System with High Light-Load Efficiency
  

  3:10 PM~3:30 PM,Tuesday , April 25

  Lee Chuang, Chun-Chang Wu, Wei-Heng Wang, and Shey-Shi Lu

  National Taiwan University, Taiwan

• D2-2 A Digitally Controlled Buck Converter with Current Sensor-less Adaptive Voltage Positioning (AVP) Mechanism
  

  3:30 PM~3:50 PM,Tuesday , April 25

  Kai-Yu Hu, Bo-Ming Chen, and Chien-Hung Tsai

  National Cheng Kung University, Taiwan

• D2-3 A 45 μW, 9.5 MHz Current-Reused RC Oscillator Using a Swing-Boosting Technique
  

  3:50 PM~4:10 PM,Tuesday , April 25

  Shao-Yung Lu and Yu-Te Liao

  National Chiao Tung University, Taiwan

• D2-4 A Current Feedback Instrumentation Amplifier with Chopping and Dynamic Element Matching Techniques and Employing the Current-Reuse Technique in Input/Feedback Stages
  

  4:10 PM~4:30 PM,Tuesday , April 25

  Tzu-Ying Chen, Yi-Ling Tsai, and Tsung-Hsien Lin

  National Taiwan University, Taiwan

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D3 ： Emerging Platform and Applications for Embedded Systems

4:50 PM~6:10 PM,Tuesday , April 25 Ballroom C

• D3-1 A Hadoop-based Principle Component Analysis on Embedded Heterogeneous Platform
  

  4:50 PM~5:10 PM,Tuesday , April 25

  Sheng-Yen Chen¹, Chia-I Wei², Yu-Chen Chiu¹, and Bo-Cheng Lai¹

  ¹National Chiao Tung University, Taiwan

  ²University of California, San Diego

• D3-2 A Body Sensor Node SoC for ECG/EMG Applications with Compressed Sensing and Wireless Powering
  

  5:10 PM~5:30 PM,Tuesday , April 25

  Yo-Hao Tu, Kai-Wen Yao, Ming-Hao Huang, Yu-Yun Lin, Hao-Yu Chi, Po-Min Cheng, Pei-Yun Tsai, Muh-Tian Shiue, Chien-Nan Liu, Kuo-Hsing Cheng, and Jia-Shiang Fu

  National Central University, Taiwan

• D3-3 An Adaptive Cross-window Stereo Camera Distance Estimation Technology and its System Implementation for Multiple Applications
  

  5:30 PM~5:50 PM,Tuesday , April 25

  Ricky Lee, Tai-En Wu, and Jiun-In Guo

  National Chiao Tung University, Taiwan

• D3-4 A Vision Radar System for Car Safety Driving Applications
  

  5:50 PM~6:10 PM,Tuesday , April 25

  Chia-Chi Tsai, Yi-Ting Lai, Yuan-Fu Li, and Jiun-In Guo

  National Chiao Tung University, Taiwan

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D5 ： Memory and Interconnection for SoC

10:20 AM~11:20 AM,Wednesday , April 26 Ballroom D

• D5-1 Design Space Exploration with a Cycle-accurate SystemC/TLM DRAM Controller Model
  

  10:20 AM~10:40 AM,Wednesday , April 26

  Ting-Shuo Hsu, Chao-Chih Wu, Che-Wei Hsu, Chih-Tsun Huang, Jing-Jia Liou, Yao-Hua Chen, and Juin-Ming Lu

  National Tsing Hua University, Taiwan

• D5-2 Reducing Aging on Scratchpad Memory Using Temporal- and FSM-based Power Management
  

  10:40 AM~11:00 AM,Wednesday , April 26

  Yun-Kae Law, Cheng-Chien Lin, and Ing-Chao Lin

  National Cheng Kung University, Taiwan

• D5-3 Optimization for Application-Specific Packet-Based On-Chip Interconnects Using a Cycle-Accurate Model
  

  11:00 AM~11:20 AM,Wednesday , April 26

  Yu-Ju Shih, Chih-Tsun Huang, Jing-Jia Liou, Jyu-Yuan Lai, Chih-Wea Wang, and Chi-Feng Wu 

  National Tsing Hua University, Taiwan 

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D6 ： Thermal- and Variation-Aware Optimization for System Designs

11:30 AM~12:30 PM,Wednesday , April 26 Ballroom D

• D6-1 A Low Power Synthesis Flow for Multi-Rate Systems
  

  11:30 AM~11:50 AM,Wednesday , April 26

  Hsin-Pang Kuo, Alan P. Su, and Kuen-Jong Lee

  National Cheng Kung University, Taiwan

• D6-2 Utilization of Relieved Corners from Multi-corner Libraries in Deterministic Static Timing Analysis
  

  11:50 AM~12:10 PM,Wednesday , April 26

  Hyun-jeong Kwon and Young-Hwan Kim

  POSTECH, Korea

• D6-3 Thermal Sensor Allocation and Full-System Temperature Characterization for Thermal-aware Mesh-based NoC System by Using Compressive Sensing Technique
  

  12:10 PM~12:30 PM,Wednesday , April 26

  Kun-Chih Chen, Yu-Hsien Chen, ana Yen-Po Lin

  National Sun Yat-Sen University, Taiwan

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D7 ： Wireless Transceiver

1:30 PM~2:30 PM,Wednesday , April 26 Ballroom C

• D7-1 A Four-band TD-LTE Transmitter with Wide Dynamic Range and LPF Bandwidth Calibration
  

  1:30 PM~1:50 PM,Wednesday , April 26

  Zhen Liang, Bin Li, Mo Huang, Hui Ye, Ken Xu, Yutao Liu, and Yan Lu

  South China University of Technology, China

• D7-2 A Digital IQ Imbalance Self-Calibration in FDD Transceiver
  

  1:50 PM~2:10 PM,Wednesday , April 26

  Hui Ye, Bin Li, Mo Huang, Zhen Liang, and Yan Lu

  South China University of Technology, China

• D7-3 A 0.9-V 2.36-GHz MedRadio-Band 10-Mbps Low-Power OOK Modulator for Neural Implants
  

  2:10 PM~2:30 PM,Wednesday , April 26

  Chien-Hua Jung and Kea-Tiong Tang

  National Tsing Hua University, Taiwan

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D9 ： Advanced Digital Systems

3:10 PM~4:30 PM,Wednesday , April 26 Ballroom C

• D9-1 A 6.4G LLR/s 8x8 64-QAM Soft-Output MIMO Detector with Lattice Reduction Preprocessing
  

  3:10 PM~3:30 PM,Wednesday , April 26

  Jing-You Lin, Jung-Chun Chi, Chun-Fu Liao, and Yuan-Hao Huang

  National Tsing Hua University, Taiwan

• D9-2 A Reference-Less All-Digital Transceiver for Human Body Channel Communication
  

  3:30 PM~3:50 PM,Wednesday , April 26

  Ching-Che Chung, Yi-Che Tsai, and Ming-Chieh Li

  National Chung Cheng University, Taiwan

• D9-3 WIDE-I/O 3D-STAKED DRAM CONTROLLER FOR NEAR-DATA PROCESSING SYSTEM
  

  3:50 PM~4:10 PM,Wednesday , April 26

  Yu-Hsuan Lin, Shih-Fan Peng, and Wei Hwang

  Nation Chiao Tung University, Taiwan

• D9-4 Analysis and Reduction of SRAM PUF Bit Error Rate
  

  4:10 PM~4:30 PM,Wednesday , April 26

  Hirofumi Shinohara, Baikun Zheng,Yanhao Piao, Bo Liu, and Shiyu Liu

  Waseda University, Japan

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D11 ： Test and Reliability for Advanced Process Technologies

4:50 PM~6:10 PM,Wednesday , April 26 Ballroom C

• D11-1 Robust Test Pattern Generation for Hold-time Faults in Nanometer Technologies
  

  4:50 PM~5:10 PM,Wednesday , April 26

  Yu-Hao Ho, Yo-Wei Chen, Chih-Ming Chang, Kai-Chieh Yang, and Chien-Mo Li

  National Taiwan University, Taiwan

• D11-2 On Designing Two-Dimensional Scan Architecture for Test Chips
  

  5:10 PM~5:30 PM,Wednesday , April 26

  Yu Huang and Wu-Tung Cheng

  Mentor Graphics, USA

• D11-3 On-Chip Temperature and Process Variation Sensing using a Reconfigurable Ring Oscillator
  

  5:30 PM~5:50 PM,Wednesday , April 26

  Tadashi Kishimoto, Tohru Ishihara, and Hidetoshi Onodera

  Kyoto University, Japan

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D14 ： Advances in Placement and Routing

10:20 AM~11:20 AM,Thursday , April 27 Mezzanine A+B

• D14-1 Detailed Routing Violation Prediction During Placement Using Machine Learning
  

  10:20 AM~10:40 AM,Thursday , April 27

  Aysa Fakheri Tabrizi, Nima Karimpour Darav, Logan Rakai, Andrew Kennings, and Laleh Behjat

  University of Calgary, Canada

• D14-2 Layout Placement Optimization with Isolation Rings for High-Voltage VLSI Circuits
  

  10:40 AM~11:00 AM,Thursday , April 27

  Chih-Wei Lee, Hwa-Yi Tseng, Chi-Lien Kuo, Chien-Nan Liu, and Chin Hsia

  National Central University, Taiwan

• D14-3 An Analytical Placer for Heterogeneous FPGAs via Rough-Placed Packing
  

  11:00 AM~11:20 AM,Thursday , April 27

  Wan-Ning Wu, Chen Chen, Ching-Yu Chin, Chun-Kai Wang, and Hung-Ming Chen

  National Chiao Tung University, Taiwan

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D15 ： ADC and PLL

11:30 AM~12:30 PM,Thursday , April 27 Mezzanine A+B

• D15-1 An 8-bit 400-MS/s Calibration-Free SAR ADC with a Pre-amplifier-only Comparator
  

  11:30 AM~11:50 AM,Thursday , April 27

  Chih-Huei Hou, Soon-Jyh Chang, Hao-Sheng Wu, Huan-Jui Hu, and En-Ze Cun

  National Cheng Kung University, Taiwan

• D15-2 A 10-bit 100-MS/s SAR ADC With Capacitor Swapping Technique in 90-nm CMOS
  

  11:50 AM~12:10 PM,Thursday , April 27

  Yung-Hui Chung and Song-You Shih

  National Taiwan University of Science and Technology, Taiwan

• D15-3 An All-Digital Phase-Locked Loop with a Multi-Delay-Switching TDC
  

  12:10 PM~12:30 PM,Thursday , April 27

  Zhong-Cheng Su and Chung-Chih Hung

  National Chiao Tung University, Taiwan

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PAGE CONTENTS

• -D1 :
   Intelligent Digital System
• -D2 :
   Analog Techniques
• -D3 :
   Emerging Platform and Applications for Embedded Systems
• -D5 :
   Memory and Interconnection for SoC
• -D6 :
   Thermal- and Variation-Aware Optimization for System Designs
• -D7 :
   Wireless Transceiver
• -D9 :
   Advanced Digital Systems
• -D11 :
   Test and Reliability for Advanced Process Technologies
• -D14 :
   Advances in Placement and Routing
• -D15 :
   ADC and PLL