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Tuesday, April 25, 1:30 PM~2:50 PM Ballroom C
D1 ： Intelligent Digital System

  • 1:30 PM~1:50 PM
    D1-1 Low-Latency Voltage-Racing Winner-Take-All (VR-WTA) Circuit for Acceleration of Learning Engine
  • 1:50 PM~2:10 PM
    D1-2 Hybrid Spiking-Stochastic Deep Neural Network
  • 2:10 PM~2:30 PM
    D1-3 Design and Implementation of a 3D Hand Gesture Architecture System Under Complicated Environment
  • 2:30 PM~2:50 PM
    D1-4 High-Speed and Low-Power VLSI-Architecture for Inexact Speculative Adder

Tuesday, April 25, 3:10 PM~4:30 PM Ballroom C
D2 ： Analog Techniques

  • 3:10 PM~3:30 PM
    D2-1 A Solar-Powered Single-Inductor Dual-Output (SIDO) DC-DC Boost for Power Management Unit System with High Light-Load Efficiency
  • 3:30 PM~3:50 PM
    D2-2 A Digitally Controlled Buck Converter with Current Sensor-less Adaptive Voltage Positioning (AVP) Mechanism
  • 3:50 PM~4:10 PM
    D2-3 A 45 μW, 9.5 MHz Current-Reused RC Oscillator Using a Swing-Boosting Technique
  • 4:10 PM~4:30 PM
    D2-4 A Current Feedback Instrumentation Amplifier with Chopping and Dynamic Element Matching Techniques and Employing the Current-Reuse Technique in Input/Feedback Stages

Tuesday, April 25, 4:50 PM~6:10 PM Ballroom C
D3 ： Emerging Platform and Applications for Embedded Systems

  • 4:50 PM~5:10 PM
    D3-1 A Hadoop-based Principle Component Analysis on Embedded Heterogeneous Platform
  • 5:10 PM~5:30 PM
    D3-2 A Body Sensor Node SoC for ECG/EMG Applications with Compressed Sensing and Wireless Powering
  • 5:30 PM~5:50 PM
    D3-3 An Adaptive Cross-window Stereo Camera Distance Estimation Technology and its System Implementation for Multiple Applications
  • 5:50 PM~6:10 PM
    D3-4 A Vision Radar System for Car Safety Driving Applications

Wednesday, April 26, 10:20 AM~11:20 AM Ballroom D
D5 ： Memory and Interconnection for SoC

  • 10:20 AM~10:40 AM
    D5-1 Design Space Exploration with a Cycle-accurate SystemC/TLM DRAM Controller Model
  • 10:40 AM~11:00 AM
    D5-2 Reducing Aging on Scratchpad Memory Using Temporal- and FSM-based Power Management
  • 11:00 AM~11:20 AM
    D5-3 Optimization for Application-Specific Packet-Based On-Chip Interconnects Using a Cycle-Accurate Model

Wednesday, April 26, 11:30 AM~12:30 PM Ballroom D
D6 ： Thermal- and Variation-Aware Optimization for System Designs

  • 11:30 AM~11:50 AM
    D6-1 A Low Power Synthesis Flow for Multi-Rate Systems
  • 11:50 AM~12:10 PM
    D6-2 Utilization of Relieved Corners from Multi-corner Libraries in Deterministic Static Timing Analysis
  • 12:10 PM~12:30 PM
    D6-3 Thermal Sensor Allocation and Full-System Temperature Characterization for Thermal-aware Mesh-based NoC System by Using Compressive Sensing Technique

Wednesday, April 26, 1:30 PM~2:30 PM Ballroom C
D7 ： Wireless Transceiver

  • 1:30 PM~1:50 PM
    D7-1 A Four-band TD-LTE Transmitter with Wide Dynamic Range and LPF Bandwidth Calibration
  • 1:50 PM~2:10 PM
    D7-2 A Digital IQ Imbalance Self-Calibration in FDD Transceiver
  • 2:10 PM~2:30 PM
    D7-3 A 0.9-V 2.36-GHz MedRadio-Band 10-Mbps Low-Power OOK Modulator for Neural Implants

Wednesday, April 26, 3:10 PM~4:30 PM Ballroom C
D9 ： Advanced Digital Systems

  • 3:10 PM~3:30 PM
    D9-1 A 6.4G LLR/s 8x8 64-QAM Soft-Output MIMO Detector with Lattice Reduction Preprocessing
  • 3:30 PM~3:50 PM
    D9-2 A Reference-Less All-Digital Transceiver for Human Body Channel Communication
  • 3:50 PM~4:10 PM
    D9-3 WIDE-I/O 3D-STAKED DRAM CONTROLLER FOR NEAR-DATA PROCESSING SYSTEM
  • 4:10 PM~4:30 PM
    D9-4 Analysis and Reduction of SRAM PUF Bit Error Rate

Wednesday, April 26, 4:50 PM~6:10 PM Ballroom C
D11 ： Test and Reliability for Advanced Process Technologies

  • 4:50 PM~5:10 PM
    D11-1 Robust Test Pattern Generation for Hold-time Faults in Nanometer Technologies
  • 5:10 PM~5:30 PM
    D11-2 On Designing Two-Dimensional Scan Architecture for Test Chips
  • 5:30 PM~5:50 PM
    D11-3 On-Chip Temperature and Process Variation Sensing using a Reconfigurable Ring Oscillator

Thursday, April 27, 10:20 AM~11:20 AM Mezzanine A+B
D14 ： Advances in Placement and Routing

  • 10:20 AM~10:40 AM
    D14-1 Detailed Routing Violation Prediction During Placement Using Machine Learning
  • 10:40 AM~11:00 AM
    D14-2 Layout Placement Optimization with Isolation Rings for High-Voltage VLSI Circuits
  • 11:00 AM~11:20 AM
    D14-3 An Analytical Placer for Heterogeneous FPGAs via Rough-Placed Packing

Thursday, April 27, 11:30 AM~12:30 PM Mezzanine A+B
D15 ： ADC and PLL

  • 11:30 AM~11:50 AM
    D15-1 An 8-bit 400-MS/s Calibration-Free SAR ADC with a Pre-amplifier-only Comparator
  • 11:50 AM~12:10 PM
    D15-2 A 10-bit 100-MS/s SAR ADC With Capacitor Swapping Technique in 90-nm CMOS
  • 12:10 PM~12:30 PM
    D15-3 An All-Digital Phase-Locked Loop with a Multi-Delay-Switching TDC

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