Best Paper Award
Starting 2009, an Award Committee is formed for the selection of the Best Paper Award each year. The selection criteria of the award include the technical contents and writing quality of the paper as well as the quality of the presentation at the symposium. The award will be presented to the selected paper in the following year's symposium.
2016 VLSI-DAT Best Paper Award Committee
Led by the Technical Program Committee co-chairs, Dr. Wu-Tung Cheng and Prof. Jiun-Lang Huang, the award committee members consist of subcommittee chairs and co-chairs. The Award Committee will select the 2016 Best Paper Award based on the criteria including the technical contents and depth, quality of the paper as well as the quality of the presentation. The award will be announced after the conference and granted in the VLSI-TSA & DAT Opening ceremony in 2017. The winner will be rewarded by a certificate and US$500 . Besides, it will also offer the registration fee waived of 2017 VLSI-DAT.
2015 Award Winners ~ Congratulations !
• A 127 fJ/conv. Continuous-Time Delta-Sigma Modulator with a DWA-Embedded Two-Step
Time-Domain Quantizer
Co-authors: Chan-Hsiang Weng, Tzu-An Wei, and Tsung-Hsien Lin
National Taiwan University, Taiwan
• Clock-Domain-Aware Test for Improving Pattern Compression
Co-authors: Kun-Han Tsai and Janusz Rajski
Mentor Graphics, USA
2016 Best Paper Candidates
• D2-1 : Architecture Agnostic Energy Model for GPU-based Design
Co-authors: Arthur Marmin, Chun-Hung Lai, Haruyuki Tago, Hsun-Lun Huang, and Juin-Ming Lu
Industrial Technology Research Institute, Taiwan
• D7-1 : Overlay-aware Layout Legalization for Self-Aligned Double Patterning Lithography
Co-authors: Chong-Meng Huang, and Shao-Yun Fang
National Taiwan University of Science and Technology, Taiwan
• D10-1 : A 12b 10MS/s 18.9fJ/Conversion-step Sub-radix-2 SAR ADC
Co-authors: Kwuang-Han Chang and Chih-Cheng Hsieh
National Tsing-Hua Univeity, Taiwan
• D12-1 : A 7 GB/S HALF-RATE CLOCK AND DATA RECOVERY CIRCUIT WITH COMPACT CONTROL
LOOP
Co-authors: Yu-Po Cheng, Yen-Long Lee, Ming-Hung Chien, and Soon-Jyh Chang
National Cheng Kung University, Taiwan
• D15-1 : A 98.6uW Acoustic Signal Processor for Fully-Implantable Cochlear Implants
Co-authors: Hao-Min Liu, Yung-Jen Lin, Yu-Chi Lee, Cheng-Yen Lee, and Chia-Hsiang Yang
National Chiao Tung University, Taiwan
• D18-1 : 28nm Ultra-Low Power Near-/Sub-threshold First-In-First-Out (FIFO) Memory for
Multi- Bio-Signal Sensing Platforms
Co-authors: Wei-Shen Hsu, Po-Tsang Huang, Shun-Lin Wu, Ching-Te Chuang, Wei Hwang,
Ming-Hsien Tu, and Ming-Yu Yin
National Chiao Tung University, Taiwan
• D19-1 : 3D-IC Test Architecture for TSVs with Different Impact Ranges of Crosstalk Faults
Co-authors: Wen Hsuan Hsu, Michael Kochte, and Kuen Jong Lee
National Cheng Kung University, Taiwan