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Monday, April 25, 1:30 PM~3:25 PM Ballroom B
T2
:
RRAM I
T2-1
ReRAM-based Analog Synapse and IMT Neuron Device for Neuromorphic System (Invited Talk)
T2-2
Oxygen chemical potential profile optimization for fast low current (<10µA) resistive switching in Oxide-based RRAM
View Biography
T2-3
Excellent Resistance Variability Control of WOx ReRAM by a Smart Writing Algorithm
View Biography
T2-4
Transient Control of Resistive Random Access Memory for High Speed and High Endurance Performance
View Biography
T2-5
A Compact Model for the SET Parameter Variations of oxide RRAM Array
View Biography
Monday, April 25, 3:50 PM~5:05 PM Ballroom B
T4
:
Novel Device I
T4-1
Self Assembled Ordered Phthalocyanine Monolayers on 2D Semiconductors for Subnanometer dielectric ALD Nucleation (Invited Talk)
T4-2
Advanced Metrology and Inspection Solutions for a 3D World (Invited Talk)
T4-3
P-type Surface Charge Transfer Doping of Black Phosphorus Field-effect Transistors
View Biography
T4-4
Performance Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits
View Biography
T4-5
Record high current density and low contact resistance in MoS2 FETs by ion doping
View Biography
Tuesday, April 26, 10:20 AM~12:00 PM Ballroom B
T5
:
CMOS
T5-1
SRAM cell performance analysis beyond 10-nm FinFET technology
View Biography
T5-2
Deep Understanding of Random Telegraph Noise (RTN) Effects on SRAM Stability
View Biography
T5-3
Investigation of Local Heating Effect for 14nm Ge pFinFETs based on Monte Carlo Method
View Biography
T5-4
Corner Spacer Design for Performance Optimization of Multi-Gate InGaAs-OI FinFET with Gate-to-Source/Drain Underlap
View Biography
T5-5
Simulation of Nano-Scale Double Gate In0.53Ga0.47As nMOSFETs by a Deterministic BTE Solver
View Biography
T5-6
Optimization of Fin Profile and Implant in Bulk FinFET Technology (Late News Paper)
Tuesday, April 26, 10:20 AM~12:15 PM Ballroom C
T7
:
3D IC I
T7-1
Key Enablers for 3D Sequential Integration (Invited Talk)
T7-2
Implementation of Memory Stacking on Logic Controller by Using 3DIC 300mm Backside TSV Process Integration
View Biography
T7-3
Impact of Transistor Technology on Power Savings in Monolithic 3D ICs
View Biography
T7-4
A-SiGeC Thin Film Photovoltaic Enabled Self-Power Monolithic 3D IC Under Indoor Illumination
View Biography
T7-5
Reliable High-Voltage Amorphous InGaZnO TFT for Monolithic 3D Integration
View Biography
Tuesday, April 26, 1:30 PM~3:10 PM Ballroom B
T8
:
Processing Technologies
T8-6
PMOS Contact Resistance Solution Compatible to CMOS Integration for 7 nm Node And Beyond (Late News Paper)
T8-1
Low Contact Resistivity (1.5×10-8 Ω-cm2) of Phosphorus-doped Ge by In-situ Chemical Vapor Deposition Doping and Laser Annealing
View Biography
T8-2
Low Temperature Microwave Annealed FinFETs with Less Vth Variability
View Biography
T8-3
In0.53Ga0.47As(001)-(2x4) and Si0.5Ge0.5(110) surface passivation by self-limiting deposition of silicon containing control layers
View Biography
T8-4
Electrical Defect Spectroscopy and Reliability Prediction Through a Novel Simulation-Based Methodology
View Biography
T8-5
RF Performance of Passive Components on State-of-Art Trap Rich Silicon- on-Insulator Substrates
View Biography
Tuesday, April 26, 1:30 PM~3:10 PM Ballroom C
T9
:
Novel Device II
T9-1
The Opportunity for bulk GaN Power Device - Technology and Application (Invited Talk)
T9-2
Short-Channel BEOL ZnON Thin-Film Transistors with Superior Mobility Performance
View Biography
T9-3
High-gain, Low-voltage BEOL Logic Gate Inverter Built with Film Profile Engineered IGZO Transistors
View Biography
T9-4
Nickel-Phosphide Contact for Effective Schottky Barrier Modulation in Black Phosphorus P-Channel Transistors
View Biography
T9-5
Experimental Demonstration of Performance Improvement with a Strain Boost Technique Tailored for 3-Dimensional Structure on Nano-Scaled Bulk pFinFETs
View Biography
T9-6
Fine charge sensing using a Silicon Nanowire for Biodetection
View Biography
Tuesday, April 26, 3:30 PM~4:30 PM Ballroom B
T10
:
NVM
T10-1
A TiO2-based Volatile Threshold Switching Selector Device with 10^7 non linearity and sub 100pA off current
View Biography
T10-2
Variable-length Gateless Transistor for Analog One-Time-Programmable Memory Applications
View Biography
T10-3
An Innovative 1T1R Dipole Dynamic Random Access Memory (DiRAM) featuring High Speed, Ultra-low power, and Low Voltage Operation
View Biography
Tuesday, April 26, 3:30 PM~4:30 PM Ballroom C
T11
:
3D IC II
T11-1
Wafer-Level MOSFET with Submicron Photolysis Polymer Temporary Bonding Technology Using Ultra-Fast Laser Ablation for 3DIC Application
View Biography
T11-2
Compact Modeling and Simulation of TSV with Experimental Verification
View Biography
T11-3
Electrical Testing Structure for Stacking Error Measurement in 3D Integration
View Biography
Wednesday, April 27, 10:20 AM~12:15 PM Ballroom C
T13
:
RRAM II
T13-1
Doping Technology for RRAM - Opportunities and Challenges (Invited Talk)
T13-2
Effect of Ti Buffer Layer on HfOx-Based Bipolar and Complementary Resistive Switching for Future Memory Applications
View Biography
T13-3
Low power/self-compliance of resistive switching elements modified with a conduction Ta-oxide layer through low temperature plasma oxidization of Ta thin film
View Biography
T13-4
Comprehensive Study of Intrinsic Unipolar SiOx-Based ReRAM Characteristics in AC Frequency Response and Low Voltage (< 2V) Operation
View Biography
T13-5
A New Manufacturing Method of CMOS Logic Compatible 1T-CRRAM
View Biography
PAGE CONTENTS
-
T2 :
RRAM I
-
T4 :
Novel Device I
-
T5 :
CMOS
-
T7 :
3D IC I
-
T8 :
Processing Technologies
-
T9 :
Novel Device II
-
T10 :
NVM
-
T11 :
3D IC II
-
T13 :
RRAM II
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