Monday, April 25, 1:30 PM~3:25 PM Ballroom B

T2 ： RRAM I

• 
  T2-1 ReRAM-based Analog Synapse and IMT Neuron Device for Neuromorphic System (Invited Talk)
  

  Kibong Moon, Euijun Cha, Daeseok Lee, Junwoo Jang, Jaesung Park, Hyunsang Hwang* 

  POSTECH, South Korea

• T2-2 Oxygen chemical potential profile optimization for fast low current (<10µA) resistive switching in Oxide-based RRAM
  

  C.Y. Chen*, **, L. Goux*, A. Fantini*, A. Redolfi*, G. Groeseneken*, **, and M. Jurczak*

  *imec, Belgium

  **KU Leuven, Belgium

• T2-3 Excellent Resistance Variability Control of WOx ReRAM by a Smart Writing Algorithm
  

  Yu-Hsuan Lin*, **, Jau-Yi Wu*, Ming-Hsiu Lee*, Tien-Yen Wang*, Yu-Yu Lin*, Feng-Ming Lee*, Dai-Ying Lee*, Erh-Kun Lai*, Kuang-Hao Chiang*, Hsiang-Lan Lung*, Kuang-Yeu Hsieh*, Tseung-Yuen Tseng**, and Chih-Yuan Lu*

  *Macronix International Co., Ltd., Taiwan

  **National Chiao Tung University, Taiwan

• T2-4 Transient Control of Resistive Random Access Memory for High Speed and High Endurance Performance
  

  Weijie Wang, Hongxin Yang, Victor Yiqian Zhuo, Minghua Li, Eng Keong Chua, and Yu Jiang

  Data Storage Institute, A*STAR, Singapore

• T2-5 A Compact Model for the SET Parameter Variations of oxide RRAM Array
  

  Lingjun Dai, Huaqiang Wu, Bin Gao, and He Qian

  Tsinghua Univeristy, China 

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Monday, April 25, 3:50 PM~5:05 PM Ballroom B

T4 ： Novel Device I

• 
  T4-1 Self Assembled Ordered Phthalocyanine Monolayers on 2D Semiconductors for Subnanometer dielectric ALD Nucleation (Invited Talk)
  

  Andrew C. Kummel

  University of California, San Diego, USA 

• 
  T4-2 Advanced Metrology and Inspection Solutions for a 3D World (Invited Talk)
  

  Ingo Schulmeyer
  Carl Zeiss Microscopy GmbH, Germany
  

• T4-3 P-type Surface Charge Transfer Doping of Black Phosphorus Field-effect Transistors
  

  Yuchen Du, Lingming Yang, Hong Zhou, and Peide D. Ye

  Purdue University, USA 

• T4-4 Performance Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits
  

  Chang-Hung Yu, Pin Su and Ching-Te Chuang

  National Chiao Tung University, Taiwan 

• T4-5 Record high current density and low contact resistance in MoS2 FETs by ion doping
  

  Sara Fathipour, Hua-Min Li, Maja Remškar*, Lingyen Yeh**, Wilman Tsai**, Yuming Lin**, Susan Fullerton-Shirey***, and Alan Seabaugh

  University of Notre Dame, USA

  *Jožef Stefan Institute, Slovenia

  **TSMC, Taiwan

  ***University of Pittsburgh, USA

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Tuesday, April 26, 10:20 AM~12:00 PM Ballroom B

T5 ： CMOS

• T5-1 SRAM cell performance analysis beyond 10-nm FinFET technology
  

  Motoi Ichihashi, Youngtag Woo, and Sanjay Parihar

  GLOBALFOUNDRIES, USA

   

• T5-2 Deep Understanding of Random Telegraph Noise (RTN) Effects on SRAM Stability
  

  Dongyuan Mao, Shaofeng Guo, Runsheng Wang, Mulong Luo*, and Ru Huang

  Peking University, China

  * University of California, San Diego, USA

• T5-3 Investigation of Local Heating Effect for 14nm Ge pFinFETs based on Monte Carlo Method
  

  Longxiang Yin, Hai Jiang, Lei Shen, Juncheng Wang, Gang Du, and Xiaoyan Liu

  Peking University, China

• T5-4 Corner Spacer Design for Performance Optimization of Multi-Gate InGaAs-OI FinFET with Gate-to-Source/Drain Underlap
  

  Vita Pi-Ho Hu, Chang-Ting Lo*, Angada B. Sachid**, Pin Su*, and Chenming Hu**

  National Central University, Taiwan

  *National Chiao Tung University, Taiwan

  **University of California, Berkeley, USA

• T5-5 Simulation of Nano-Scale Double Gate In0.53Ga0.47As nMOSFETs by a Deterministic BTE Solver
  

  Shaoyan Di*, Kai Zhao*,**, Zhiyuan Lun*, Tiao Lu*, Gang Du*, and Xiaoyan Liu*

  *Peking University, China

  **Beijing Information Science and Technology University, China

• T5-6 Optimization of Fin Profile and Implant in Bulk FinFET Technology (Late News Paper)
  

  Y.-S. Wu, C.-H.Tsai, T. Miyashita, P.-N. Chen, B.-C. Hsu, P.-H. Wu, H.-H. Hsu, C.-Y. Chiang, H.-H. Liu, H.-L.Yang, K.-C Kwong, J.-C. Chiang, C.-W. Lee, Y.-J. Lin, C.-A. Lu, C.-Y. Lin, and S.-Y. Wu

  TSMC, Taiwan

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Tuesday, April 26, 10:20 AM~12:15 PM Ballroom C

T7 ： 3D IC I

• 
  T7-1 Key Enablers for 3D Sequential Integration (Invited Talk)
  

  Laurent Brunet

  Cea Leti, France

• T7-2 Implementation of Memory Stacking on Logic Controller by Using 3DIC 300mm Backside TSV Process Integration
  

  Shang-Chun Chen, Pei-Jer Tzeng, Yu-Chen Hsin, Chung-Chih Wang, Po-Chih Chang, Jui-Chin Chen, Yiu-Hsiang Chang, Tsuen-Sung Chen, Tzu-Chien Hsu, Hsiang-Hung Chang, Chau-Jie Zhan, Chia-Hsin Lee, Yung-Fa Chou, Ding-Ming Kwai, Tzu-Kun Ku, Pei-Hua Wang, and We-Chung Lo

  Industrial Technology Research Institute, Taiwan

• T7-3 Impact of Transistor Technology on Power Savings in Monolithic 3D ICs
  

  Sandeep Kumar Samal*,**, Deepak Kumar Nayak*, Motoi Ichihashi*, Srinivasa Banna*, and Sung Kyu Lim**

  *GLOBALFOUNDRIES, USA

  **Georgia Institute of Technology, USA

• T7-4 A-SiGeC Thin Film Photovoltaic Enabled Self-Power Monolithic 3D IC Under Indoor Illumination
  

  Ming-Hsuan Kao*, Chih-Chao Yang**, Tsung-Ta Wu**, Tung-Ying Hsieh**, Wen-Hsien Huang**, Hsing-Hsiang Wang**, Chang-Hong Shen**, Wen-Kuan Yeh**, Meng-Fan Chang***, and Jia-Min Shieh*,**

  *National Chiao Tung University, Taiwan

  **National Nano Device Laboratories, Taiwan

  ***National Tsing Hua University, Taiwan

• T7-5 Reliable High-Voltage Amorphous InGaZnO TFT for Monolithic 3D Integration
  

  Ming-Jiue Yu, Ruei-Ping Lin, Yu-Hong Chang, and Tuo-Hung Hou

  National Chiao Tung University, Taiwan

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Tuesday, April 26, 1:30 PM~3:10 PM Ballroom B

T8 ： Processing Technologies

• T8-1 Low Contact Resistivity (1.5×10-8 Ω-cm2) of Phosphorus-doped Ge by In-situ Chemical Vapor Deposition Doping and Laser Annealing
  

  S. -H. Huang*, F. -L. Lu*, and C. W. Liu*, **

  *National Taiwan University, Taiwan

  ** National Nano Device Laboratories, Taiwan

• T8-2 Low Temperature Microwave Annealed FinFETs with Less Vth Variability
  

  K. Endo, Y. -J Lee*, Y. Ishikawa, F. -K. Hsueh*, P. -J. Sung*, Y. -X. Liu, T. Matsukawa, S. O'uchi, J. Tsukada, H. Yamauchi, and M. Masahara

  National Institute of Advanced Industrial Science and Technology, Japan

  * National Nano Device Laboratories, Taiwan

• T8-3 In0.53Ga0.47As(001)-(2x4) and Si0.5Ge0.5(110) surface passivation by self-limiting deposition of silicon containing control layers
  

  M. Edmonds, T. J. Kent, S. Wolf, K. Sardashti, M. Chang*, J. Kachian*, R. Droopad**, E. Chagarov, and A. C. Kummel

  University of California, San Diego, USA

  *Applied Materials, USA

  **Texas State University, USA

• T8-4 Electrical Defect Spectroscopy and Reliability Prediction Through a Novel Simulation-Based Methodology
  

  L. Larcher*,**, G. Sereni*, A. Padovani*,**, and L. Vandelli*,**

  *University of Modena and Reggio Emilia, Italy

  **MDLab s.r.l., Italy

• T8-5 RF Performance of Passive Components on State-of-Art Trap Rich Silicon- on-Insulator Substrates
  

  Lei Zhu*,**, Shuangke Liu*, F. Allibert***, E. Desbonnets***, I. Radu***, Xinen Zhu* and Yumin Lu*,**

  *Shanghai Industrial uTechnology Research Institute, China

  **Shanghai Institute of Microsystem and Information Technology, China

  ***SOITEC, France

• T8-6 PMOS Contact Resistance Solution Compatible to CMOS Integration for 7 nm Node And Beyond (Late News Paper)
  

  C.-N. Ni, Y.-C. Huang, S. Jun, S. Sun, A. Vyas, F. Khaja, K.V. Rao, S. Sharma, N. Breil, M. Jin, C. Lazik, A. Mayur, J. Gelatos, H. Chung, R. Hung, M. Chudzik, N. Yoshida, and N. Kim

  Applied Materials, USA

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Tuesday, April 26, 1:30 PM~3:10 PM Ballroom C

T9 ： Novel Device II

• 
  T9-1 The Opportunity for bulk GaN Power Device - Technology and Application (Invited Talk)
  

  Zhen-Yu Li

  HUGA OPTOTECH INC., Taiwan

• T9-2 Short-Channel BEOL ZnON Thin-Film Transistors with Superior Mobility Performance
  

  Chin-I Kuan, Horng-Chih Lin, Pei-Wen Li, and Tiao-Yuan Huang

  National Chiao Tung University, Taiwan

• T9-3 High-gain, Low-voltage BEOL Logic Gate Inverter Built with Film Profile Engineered IGZO Transistors
  

  Rong-Jhe Lyu, Yun-Hsuan Chiu, Horng-Chih Lin, Pei-Wen Li, and Tiao-Yuan Huang

  National Chiao Tung University, Taiwan 

• T9-4 Nickel-Phosphide Contact for Effective Schottky Barrier Modulation in Black Phosphorus P-Channel Transistors
  

  Zhi-Peng Ling, Kausik Majumdar*, Soumya Sakar, Sinu Mathew, Jun-Tao Zhu, K. Gopinadhan, T. Venkatesan, and Kah-Wee Ang

  National University of Singapore, Singapore

  *Indian Institute of Science, India

• T9-5 Experimental Demonstration of Performance Improvement with a Strain Boost Technique Tailored for 3-Dimensional Structure on Nano-Scaled Bulk pFinFETs
  

  Ta-Chun Lin, Yun-Ju Sun, Ming-Huei Lin, Tomonari Yamamoto, and Shyh-Horng Yang

  Taiwan Semiconductor Manufacturing Company, Taiwan

• T9-6 Fine charge sensing using a Silicon Nanowire for Biodetection
  

  Corentin Carmignani, Olivier Rozeau, Pascal Scheiblin, Aurélie Thuaire, Patrick Reynaud, Sylvain Barraud, Thomas Ernst, Severine Cheramy, and Maud Vinet

  Cea Leti, France

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Tuesday, April 26, 3:30 PM~4:30 PM Ballroom B

T10 ： NVM

• T10-1 A TiO2-based Volatile Threshold Switching Selector Device with 10^7 non linearity and sub 100pA off current
  

  Simone Cortese, Maria Trapatseli, Ali Khiat, and Themistoklis Prodromakis

  University of Southampton, United Kingdom

• T10-2 Variable-length Gateless Transistor for Analog One-Time-Programmable Memory Applications
  

  Po-Ruei Cheng, Chih-Sung Yang, Meng-Yin Hsu, Chrong Jung Lin, and Ya-Chin King

  National Tsing-Hua University, Taiwan

• T10-3 An Innovative 1T1R Dipole Dynamic Random Access Memory (DiRAM) featuring High Speed, Ultra-low power, and Low Voltage Operation
  

  E. R. Hsieh, C. H. Chuang, and Steve S. Chung

  National Chiao Tung University, Taiwan

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Tuesday, April 26, 3:30 PM~4:30 PM Ballroom C

T11 ： 3D IC II

• T11-1 Wafer-Level MOSFET with Submicron Photolysis Polymer Temporary Bonding Technology Using Ultra-Fast Laser Ablation for 3DIC Application
  

  Chuan-An Cheng, Yu-Hsiang Huang, Chien-Hung Lin*, Chia-Lin Lee*, Shan-Chun Yang*, and Kuan-Neng Chen

  National Chiao Tung University, Taiwan

  *Kingyoup Optronics Co., Ltd, Taiwan

• T11-2 Compact Modeling and Simulation of TSV with Experimental Verification
  

  Jhih-Yang Yan, Sun-Rong Jan, Yi-Chung Huang, Huang-Siang Lan, C. W. Liu, Y.-H. Huang*, Bigchoug Hung*, K.-T. Chan*, Michael Huang*, and M.-T. Yang*

  National Taiwan University, Taiwan

  *MediaTek Inc., Taiwan

• T11-3 Electrical Testing Structure for Stacking Error Measurement in 3D Integration
  

  Shih-Wei Lee, Shu-Chiao Kuo, and Kuan-Neng Chen

  National Chiao Tung University, Taiwan

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Wednesday, April 27, 10:20 AM~12:15 PM Ballroom C

T13 ： RRAM II

• 
  T13-1 Doping Technology for RRAM - Opportunities and Challenges (Invited Talk)
  

  Blanka Magyari-Köpe*, Dan Duncan, Liang Zhao, and Yoshio Nishi

  Stanford University, USA

• T13-2 Effect of Ti Buffer Layer on HfOx-Based Bipolar and Complementary Resistive Switching for Future Memory Applications
  

  Sk. Ziaur Rahaman, Yu-De Lin, Pei-Yi Gu, Heng-Yuan Lee, Yu-Sheng Chen, Pan-Shiu Chen*, Kan-Hsueh Tsai, Wei-Su Chen, Chien-Hua Hsu, Po-Tsung Tu, Frederick T. Chen, Ming-Jinn Tsai, Tzu-Kun Ku, and Pei-Hua Wang

  Industrial Technology Research Institute, Taiwan

  *MingShin University of Science and Technology, Taiwan

• T13-3 Low power/self-compliance of resistive switching elements modified with a conduction Ta-oxide layer through low temperature plasma oxidization of Ta thin film
  

  Yu-Sheng Chen, Heng-Yuan Lee, Pang-Shiu Chen*, Y. D. Lin, Kan-Hsueh Tsai, C.H. Hsu, W. S. Chen, Ming-Jinn Tsai, T. K. Ku, and P. H. Wang

  Industrial Technology Research Institute, Taiwan

  *MingShin University of Science and Technology, Taiwan

• T13-4 Comprehensive Study of Intrinsic Unipolar SiOx-Based ReRAM Characteristics in AC Frequency Response and Low Voltage (< 2V) Operation
  

  Ying-Chen Chen, Yao-Feng Chang, Burt Fowler, Fei Zhou, Xiaohan Wu, Cheng-Chih Hsieh, Heng-Lu Chang, Chih-Hung Pan*, Min-Chen Chen*, Kuan-Chang Chang*, Tsung-Ming Tsai*, Ting-Chang Chang*, and Jack C. Lee

  The University of Texas at Austin, USA

  *National Sun Yat-Sen University , Taiwan

• T13-5 A New Manufacturing Method of CMOS Logic Compatible 1T-CRRAM
  

  Hung-Yu Chen, Hsien-Hao Chen, Yun-Feng Kao, Ping-Yu Chen, Ya-Chin King, and Chrong Jung Lin

  National Tsing-Hua University, Taiwan

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PAGE CONTENTS

• -T2 :
   RRAM I
• -T4 :
   Novel Device I
• -T5 :
   CMOS
• -T7 :
   3D IC I
• -T8 :
   Processing Technologies
• -T9 :
   Novel Device II
• -T10 :
   NVM
• -T11 :
   3D IC II
• -T13 :
   RRAM II