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Monday, April 25, 1:30 PM~2:50 PM Ballroom D ( 11F )
D1
:
Sub-Systems for Medical Applications
1:30 PM~1:50 PM
D1-1
A 13.56-MHz Passive NFC Tag IC in 0.18-μm CMOS Process for Biomedical Applications
View Biography
1:50 PM~2:10 PM
D1-2
Multiple Output Switched Capacitor DC-DC Converter with Capacitor Sharing for Sensor-Fusion Platforms
View Biography
2:10 PM~2:30 PM
D1-3
A Low-Power Oscillator-Based Readout Interface for Medical Ultrasonic Sensors
View Biography
Monday, April 25, 3:10 PM~4:30 PM Ballroom D ( 11F )
D2
:
Design and Implementation for Many-Core Systems
3:10 PM~3:30 PM
D2-1
Architecture Agnostic Energy Model for GPU-based Design
View Biography
3:30 PM~3:50 PM
D2-2
Sniper-TEVR: Core-Variation Simulation Platform with Register-Level Fault Injection for Robust Computing in CMP System
View Biography
3:50 PM~4:10 PM
D2-3
Interference-Aware Batch Memory Scheduling in Heterogeneous Multicore Architecture
View Biography
4:10 PM~4:30 PM
D2-4
Scalable Mutli-Layer Barrier Synchronization on NoC
View Biography
Monday, April 25, 4:50 PM~6:10 PM Ballroom D ( 11F )
D5
:
Intelligent and Efficient System Design
4:50 PM~5:10 PM
D5-1
Microcontroller Implementation of Low-Power Compression for Wearable Biosignal Transmitter
View Biography
5:10 PM~5:30 PM
D5-2
An Efficient and Effective Performance Estimation Method for DSE
View Biography
5:30 PM~5:50 PM
D5-3
A Smart Surveillance System with Multiple People Detection, Tracking, and Behavior Analysis
View Biography
5:50 PM~6:10 PM
D5-4
Design and Implementation of a Dangerous Driving Behavior Analysis System
View Biography
Tuesday, April 26, 10:20 AM~11:20 AM Ballroom D ( 11F )
D6
:
Low-Power Low-Voltage Analog Circuit Designs
10:20 AM~10:40 AM
D6-1
A 70nW, 0.3V Temperature Compensation Voltage Reference Consisting of Subthreshold MOSFETs in 65nm CMOS Technology
View Biography
10:40 AM~11:00 AM
D6-2
A Precise Decibel-Linear Programmable-Gain Amplifier for Ultrasound Imaging Receivers
View Biography
11:00 AM~11:20 AM
D6-3
An Analog Front-End with Fast Motion Artifact Recovery for Bio-Signal Recording
View Biography
Tuesday, April 26, 10:20 AM~11:20 AM Mezzanine A+B ( 13F )
D7
:
Advances in Lithography
10:20 AM~10:40 AM
D7-1
Overlay-aware Layout Legalization for Self-Aligned Double Patterning Lithography
View Biography
10:40 AM~11:00 AM
D7-2
Trim Mask Optimization for Hybrid Multiple Pattering Lithography
View Biography
11:00 AM~11:20 AM
D7-3
A Lithographic Mask Manufacturability and Pattern Fidelity Aware OPC Algorithm
View Biography
Tuesday, April 26, 11:30 AM~12:30 PM Ballroom D ( 11F )
D8
:
Low-Power / High-Performance VLSI Architecture
11:30 AM~11:50 AM
D8-1
An Energy-Efficient Nonvolatile Microprocessor Considering Software-Hardware Interaction for Energy Harvesting Applications
View Biography
11:50 AM~12:10 PM
D8-2
High Performance VLSI Architecture for 3-D Discrete Wavelet Transform
View Biography
12:10 PM~12:30 PM
D8-3
A Variable-Latency, Ultra-Low-Voltage RISC Processor with a New In-Situ Error Detection and Correction Techniques
View Biography
Tuesday, April 26, 11:30 AM~12:30 PM Mezzanine A+B ( 13F )
D9
:
Advanced TPG Technologies
11:30 AM~11:50 AM
D9-1
Test Coverage Debugging for Designs with Timing Exception Paths
View Biography
11:50 AM~12:10 PM
D9-2
An IR-Drop Guided Test Pattern Generation Technique
View Biography
12:10 PM~12:30 PM
D9-3
On Gate Function Based Tests for Scan Designs
View Biography
Tuesday, April 26, 1:30 PM~2:50 PM Ballroom D ( 11F )
D10
:
Data Converters and Circuit Techniques
1:30 PM~1:50 PM
D10-1
A 12b 10MS/s 18.9fJ/Conversion-Step Sub-Radix-2 SAR ADC
View Biography
1:50 PM~2:10 PM
D10-2
A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS Process
View Biography
2:10 PM~2:30 PM
D10-3
DAC Linearity Improvement Algorithm With Unit Cell Sorting Based on Magic Square
View Biography
2:30 PM~2:50 PM
D10-4
Fundamental Design Consideration of Sampling Circuit
View Biography
Tuesday, April 26, 1:30 PM~2:50 PM Mezzanine A+B ( 13F )
D11
:
Digital Communication Systems
1:30 PM~1:50 PM
D11-1
Linear Precoding and Adaptive Multi-Taper Spectrum Detector for Cognitive Radios
View Biography
1:50 PM~2:10 PM
D11-2
Temperature Tracking Scheme for Programmable Phase-Shifter in Pulsed Radar SoC
View Biography
2:10 PM~2:30 PM
D11-3
Time-Domain Characteristics of Body Channel Communication (BCC) and BCC Transceiver Design
View Biography
Tuesday, April 26, 3:10 PM~4:30 PM Ballroom D ( 11F )
D12
:
Fast Transceiver Circuit Techniques
3:10 PM~3:30 PM
D12-1
A 7 GB/S Half-Rate Clock and Data Recovery Circuit with Compact Control Loop
View Biography
3:30 PM~3:50 PM
D12-2
A 2x25Gb/s 20mW Serializing Transmitter with 2.5:1 Multiplexers in 40nm Technology
View Biography
3:50 PM~4:10 PM
D12-3
A Hybrid Frequency/Phase-Locked Loop for Versatile Clock Generation with Wide Reference Frequency Range
View Biography
4:10 PM~4:30 PM
D12-4
The LED Driver IC of Visible Light Communication with High Data Rate and High Efficiency
View Biography
Tuesday, April 26, 3:10 PM~4:30 PM Mezzanine A+B ( 13F )
D13
:
Advances in Layout Synthesis
3:10 PM~3:30 PM
D13-1
An Integrated Placement and Routing for Ratioed Capacitor Array based on ILP Formulation
View Biography
3:30 PM~3:50 PM
D13-2
Automatic Synthesis Flow for Voltage Rectifiers with Impedance Consideration
View Biography
3:50 PM~4:10 PM
D13-3
Area Minimization Method for CMOS Circuits Using Constraint Programming in 1D-Layout Style
View Biography
4:10 PM~4:30 PM
D13-4
ThermPL: Thermal-Aware Placement Based on Thermal Contribution and Locality
View Biography
Wednesday, April 27, 10:20 AM~11:20 AM Ballroom D ( 11F )
D15
:
Biomedical Circuits and Systems
10:20 AM~10:40 AM
D15-1
A 98.6uW Acoustic Signal Processor for Fully-Implantable Cochlear Implants
View Biography
10:40 AM~11:00 AM
D15-2
A 1.4 mW Low-Power Feed-Back FxLMS ANC VLSI Design for In-Ear Headphones
View Biography
11:00 AM~11:20 AM
D15-3
A Multi-Axis Readout Circuit Using in Female Ovulation Monitoring Platform
View Biography
Wednesday, April 27, 10:20 AM~11:20 AM Mezzanine A+B ( 13F )
D16
:
System-Level Synthesis and Design
10:20 AM~10:40 AM
D16-1
2.5D System Synthesis Methodology under Performance, Power and Thermal Constraints
View Biography
10:40 AM~11:00 AM
D16-2
Guidelines for Effective and Simplified Dynamic Supply and Threshold Voltage Scaling
View Biography
11:00 AM~11:20 AM
D16-3
A High-Level Synthesis Algorithm for FPGA Designs Optimizing Critical Path with Interconnection-Delay and Clock-Skew Consideration
View Biography
Wednesday, April 27, 11:30 AM~12:30 PM Ballroom D ( 11F )
D18
:
Nanometer Memory Designs
11:30 AM~11:50 AM
D18-1
28nm Ultra-Low Power Near-/Sub-threshold First-In-First-Out (FIFO) Memory for Multi-Bio-Signal Sensing Platforms
View Biography
11:50 AM~12:10 PM
D18-2
A 128-kb 25% Power Reduced 1T High Density ROM with 0.55 ns Access Time using Low Swing Bitline Edge Sensing in 16nm FinFET Technology
View Biography
12:10 PM~12:30 PM
D18-3
A 1V 800MHz 140Kb Register File Compiler using Variation Aware Self-Timing in 40nm Bulk CMOS
View Biography
Wednesday, April 27, 11:30 AM~12:30 PM Mezzanine A+B ( 13F )
D19
:
Emerging Technologies for Highly Reliable System
11:30 AM~11:50 AM
D19-1
3D-IC Test Architecture for TSVs with Different Impact Ranges of Crosstalk Faults
View Biography
11:50 AM~12:10 PM
D19-2
SERL: Soft Error Resilient Latch Design
View Biography
12:10 PM~12:30 PM
D19-3
A Test-per-Cycle BIST Architecture with Low Area Overhead and No Storage Requirement
View Biography
PAGE CONTENTS
-
D1 :
Sub-Systems for Medical Applications
-
D2 :
Design and Implementation for Many-Core Systems
-
D5 :
Intelligent and Efficient System Design
-
D6 :
Low-Power Low-Voltage Analog Circuit Designs
-
D7 :
Advances in Lithography
-
D8 :
Low-Power / High-Performance VLSI Architecture
-
D9 :
Advanced TPG Technologies
-
D10 :
Data Converters and Circuit Techniques
-
D11 :
Digital Communication Systems
-
D12 :
Fast Transceiver Circuit Techniques
-
D13 :
Advances in Layout Synthesis
-
D15 :
Biomedical Circuits and Systems
-
D16 :
System-Level Synthesis and Design
-
D18 :
Nanometer Memory Designs
-
D19 :
Emerging Technologies for Highly Reliable System
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