DAT Best Paper Award
Starting 2009, an Award Committee is formed for the selection of the Best Paper Award each year. The selection criteria of the award include the technical contents and writing quality of the paper as well as the quality of the presentation at the symposium. The award will be presented to the selected paper in the following year's symposium.
DAT Best Paper Award Committee
Led by the DAT Program Chairs, Dr. Shigeki Tomishima, Prof. Chih-Wei Liu and Prof. Ming-Der Shieh, the award committee members consist of subcommittee co-chairs. The Award Committee will select the 2024 DAT Best Paper Award based on the criteria including the technical contents and depth, quality of the paper as well as the quality of the presentation. The award will be announced after the conference and granted in the International VLSI Symposium on Technology, Systems and Applications opening ceremony in 2025. The winner will be rewarded by a certificate and US$500 . Besides, it will also offer the registration fee waived of 2025 International VLSI Symposium on Technology, Systems and Applications.
2023 DAT Best Paper Award Winners ~ Congratulations!
The 2023 DAT Best Paper Award will be granted in International VLSI Symposium on Technology, Systems and Applications opening ceremony in 2024 and the winner will be rewarded by a certificate and US$500. Besides, it will also offer the registration fee waived of 2024 International VLSI Symposium on Technology, Systems and Applications.
• A 7~10.5-Gb/s Reference-Less Linear Half-rate CDR Circuit Using Automatic Band Selector
Co-authors: Yi-En Hsu and Shen-Iuan Liu
National Taiwan University
• A Built-In Self-Calibration Scheme for Memristor-Based Spiking Neural Networks
Co-authors: Chi Tung, Kuan-Wei Hou and Cheng-Wen Wu
National Tsing Hua University
2024 DAT Best Paper Award Candidates
• D1-1 A 14.7-20-Gb/s Reference-Less Baud-rate CDR Circuit with One-Tap DFE and Time-Interpolation
Co-authors: Po-Yuan Chou and Shen-Iuan Liu
National Taiwan University
• D2-1 VLSI Design of a Fast and Area-Efficient Haze Removal Method Based on Color Attenuation Prior
Co-authors: Yueh-Chan Lee and Ren-Der Chen
National Changhua University of Education
• D2-2 AI-ISP Accelerator with RISC-V ISA Extension for Image Signal Processing
Co-authors: Zong-Mao Wu1, Yu-Chi Lin1 and Chih-Wei Liu1,2
1 National Yang Ming Chiao Tung University
2 Industrial Technology Research Institute
• D4-4 Set-Pair Routing Solver with Layer-by-layer Formulation on ILP
Author: Yasuhiro Takashima
The University of Kitakyushu
• D6-1 QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL
Co-authors: Lennart M. Reimann1, Anshul Prashar1, Chiara Ghinami1, Rebecca Pelke1, Dominik Sisejkovic2, Farhad Merchant3 and Rainer Leupers1
1 RWTH Aachen University
2 Robert Bosch GmbH
3 Newcastle University
• D6-3 Branch-Aware Self-Test Program Generation for Processor Cores
Co-authors: Li-An Kuo and Jiun-Lang Huang
National Taiwan University
• D7-1 A Latch-based Stochastic Number Generator for Stochastic Computing of Extended Naïve Bayesian Network
Co-authors: Ruilin Zhang1,2, Xiaoyang Jun3, Jiawei Liu4, Xingyu Wang2, Shufan Xu1, Kunyang Liu2, Shinichi Nishizawa2, Kiichi Niitsu1 and Hirofumi Shinohara2
1 Kyoto University
2 Waseda University
3 Lenovo
4 China Construction Bank