Winners of TSA Best Student Paper Award
2021 :
Yueh-Hua Chu, National Chiao Tung University
"Ultra-thin Hf0.5Zr0.5O2 Ferroelectric Tunnel Junction with High Current Density"
Co-authors: Hsin-Hui Huang1, Yu-Hao Chen1, Chien-Hua Hsu2, Pei-Jer Tzeng2, Shyh-Shyuan Sheu2, Wei-Chung Lo2, Chih-I Wu2,3, and Tuo-Hung Hou1,2
1National Chiao Tung University, 2Industrial Technology Research Institute, and 3National Taiwan University
Franz Müller, Fraunhofer IPMS-CNT, Germany"
Current percolation path impacting switching behavior of ferroelectric FETs"
Maximilian Lederer1, Ricardo Olivo1, Tarek Ali1, Raik Hoffmann1, Halid Mulaosmanovic2, Sven Beyer3, Stefan Dünkel3, Johannes Müller3, Stefan Müller4, Konrad Seidel1, Gerald Gerlach5
1Fraunhofer IPMS-CNT, Germany, 2NaMLab gGmbH, Germany, 3GLOBALFOUNDRIES, Germany, 4Ferroelectric Memory GmbH, Germany, and 5Technische Universität Dresden, Germany
2020 :
Shen-Yang Lee, National Yang Ming Chiao Tung University
"Investigation of the Impact of Internal Metal Gate — From MFM Capacitors to Two-Layer-Stacked GAA Poly-Si NW FE-FETs"
Co-authors: Shen-Yang Lee1, Han-Wei Chen1, Chun-Chih Chung1, Chiuan-Huei Shen1, Po-Yi Kuo2, Yu-En Huang1, Hsin-Yu Chen1, and Tien-Sheng Chao1
1National Chiao Tung University, and 2Feng Chia University
2019 :
Daphnée Bosch, CEA-LETI, Univ. Grenoble Alpes, France; Univ. Grenoble Alpes, CNRS, Grenoble INP, IMEP-LAHC, France
"Novel Fine-Grain Back-Bias Assist Techniques for 14nm FDSOI Top-Tier SRAMs integrated in 3D-Monolithic"
Co-Authors: F. Andrieu1, L. Ciampolini1, 2, A. Makosiej1, O. Weber1,2, X. Garros1, J. Lacord1, J. Cluzel1, E. Esmanhotto1, M. Rios1, S. Lang1, B. Giraud1, R. Berthelon2, G. Cibrario1, L. Brunet1, P. Batude1, C. Fenouillet-Béranger1, D. Lattard1, J. P. Colinge1, F. Balestra3, M. Vinet1
1CEA-LETI, Univ. Grenoble Alpes, France; 2STMicroelectronics, France; 3Univ. Grenoble Alpes, CNRS, Grenoble INP, IMEP-LAHC, France
Ava J. Tan, University of California Berkeley, USA; Lam Research Corporation, USA
“Ferroelectric Si-doped HfO2 Capacitors for Next-Generation Memories”
Co-Authors: Zhongwei Zhu2, Hwan Sung Choe2, Chenming Hu1, Sayeef Salahuddin1, Alex Yoon2
1University of California Berkeley, USA, 2Lam Research Corporation, USA
2018 :
Chun-Li Lo, Purdue University University, USA
"BEOL Compatible Sub-nm Diffusion Barrier for Advanced Cu Interconnects"
Co-Authors: Kehao Zhang, Joshua A. Robinson, The Pennsylvania State University, USA and Zhihong Chen, Purdue University, USA
Yu-Ting Peng, University of Illinois Urbana-Champaign, USA
"All Optical NOR Gate via Tunnel-Junction Transistor Lasers for High Speed Optical Logic Processors"
Co-Authors: Milton Feng, Ardy Winoto, Junyi Qiu, Yu-Ting Peng and Nick Holonyak, Jr., University of Illinois Urbana-Champaign
2017 :
Chih-Yang Lin, National Sun Yat-Sen University, Taiwan
"A Universal Model for Interface-type Threshold Switching Phenomena by Comprehensive Study of Vanadium Oxide-Based Selector"
Co-Authors: Ying-Chen Chen, Meiqi Guo, Chih-Hung Pan, Fu-Yuan Jin, Yi-Ting Tseng, Cheng Chih Hsieh, Xiaohan Wu, Min-Chen Chen, Yao-Feng Chang,
Fei Zhou,
Burt Fowler, Kuan-Chang Chang,
Simon M. Sze, Sanjay Banerjee
Yu-Hung Yeh, National Tsing Hua University, Taiwan
"An Investigation of Program Disturb Characteristics and
Data Pattern Effect in 128G 3D NAND Flash Memories"
Co-Authors: Sheng-Hung Shih, Jen-Chien Fu, Chrong-Jung Lin
and Ya-Chin King
2016 :
Ming-Hsuan Kao, National Chiao Tung University, Taiwan
"A-SiGeC Thin Film Photovoltaic Enabled Self-Power Monolithic 3D IC Under Indoor Illumination"
Co-Authors: Chih-Chao Yang, Tsung-Ta Wu, Tung-Ying Hsieh, Wen-Hsien Huang, Hsing-Hsiang Wang, Chang-Hong Shen, Wen-Kuan Yeh, Meng-Fan Chang, and Jia-Min Shieh
Rong-Jhe Lyu, National Chiao Tung University, Taiwan
"High-gain, Low-voltage BEOL Logic Gate Inverter Built with Film Profile Engineered IGZO Transistors
"
Co-Authors: Yun-Hsuan Chiu, Horng-Chih Lin, Pei-Wen Li, and Tiao-Yuan Huang
2015 :
Cheng-Ying Huang, University of California Santa Barbara, USA
"Ultrathin InAs-Channel MOSFETs on Si substrates"
Co-Authors: Xinyu Bao, Zhiyuan Ye, Sanghoon Lee, Hanwei Chiang, Haoran Li, Varistha Chobpattana, Brian Thibeault, William Mitchell, Susanne Stemmer, Arthur Gossard, Errol Sanchez, and Mark Rodwell
M. Edmonds, University of California San Diego , USA
"Passivation of surface defects on InGaAs (001) and (110) surfaces in preparation for subsequent gate oxide ALD"
Co-Authors: T. J Kent, M. Chang, J.Kachian, R.Droopad, E. Chagarov, and A. C. Kummel
2014 : Abhishek A. Sharma, Carnegie Mellon University, USA
"High-Speed In-situ Pulsed Thermometry in Oxide RRAMs"
Co-Authors: Mohammad Noman, Marek Skowronski, James A. Bain
Liang Zhao, Stanford University, USA
"Improved Multi-level Control of RRAM Using Pulse-Train Programming"
Co-Authors: Hong-Yu Chen, Shih-Chieh Wu, Zizhen Jiang, Shimeng Yu, Tuo-Hung Hou,
H.-S. Philip Wong, and Yoshio Nishi
2013 :
Chun Wing Yeung, University of California, Berkeley, USA
"Low Power Negative Capacitance FETs for Future Quantum-Well Body Technology"
Co-Authors: Asif I. Khan, Asis Sarker, Sayeef Salahuddin, and Chenming Hu
Chunlei Zhan, National University of Singapore, Singapore
"(110)-Oriented Germanium-Tin (Ge0.97Sn0.03) P-channel MOSFETs"
Co-Authors: Wei Wang, Xiao Gong, Pengfei Guo, Bin Liu, Yue Yang, Genquan Han, and Yee-Chia Yeo
2012 :
Jing Wan, IMEP-LAHC, France
"Z2-FET: A zero-slope switching device with gate-controlled hysteresis"
Co-Authors: J. Wan, C. Le Royer, A. Zaslavsky, S. Cristoloveanu
2011 :
Shao-Ming Koh, National University of Singapore, Singapore
"New Tellurium Implant and Segregation for Contact Resistance Reduction and Single Metallic Silicide Technology for Independent Contact Resistance Optimization in n- and p-FinFETs"
Co-Authors: Eugene Yu Jin Kong, Bin Liu, Chee-Mang Ng, Pan Liu, Zhi-Qiang Mo, Kam-Chew Leong, Ganesh S. Samudra, and Yee-Chia Yeo
2010 :
Jean-Luc Huguenin, ST Microelectronics, IMEP, France
"Localized SOI Logic and Bulk I/O devices co-integration for Low Power System-on-Chip Technology”
Co-Authors: J.-L. Huguenin, S. Monfray, S. Denorme, G. Bidal, P. Perreau, S. Barnola, M.-P. Samson, K. Benotmane, N. Loubet, Y. Campidelli, F. Leverd, F. Abbate, L. Clement, C. Borowiak, Dominique Golanski, C. Fenouillet-Beranger, F. Boeuf, G. Ghibaudo, T. Skotnicki
2009 :
Dominique Fleury, STMicroelectronics, IMEP-LAHC laboratory, France
“A New Technique to Extract the Gate Bias Dependent S/D Series Resistance of Sub-100nm MOSFETs”
Co-Authors: Antoine Cros, Gregory Bidal, Hugues Brut, Emmanuel Josse and Gerard Ghibaudo
2008 :
Eng-Huat Toh, National University of Singapore
“P-Channel I-MOS Transistor featuring Silicon Nano-Wire with Multiple-Gates, Si1-yCy I-region, in situ doped Si1-yCy Source, and Sub-5 mV/decade Subthreshold Swing”
Co-Authors: Grace Huiqi Wang, Doran Weeks, Ming Zhu, Trevan Landin, Jennifer Spear, Lap Chan, Shawn G. Thomas, Ganesh Samudra, and Yee-Chia Yeo
2007 :
Donovan Lee, University of California at Berkeley
“WetFET – A Novel Fluidic Gate-Dielectric Transistor for Sensor Application”
Co-Authors: Xin Sun, Emmanuel Quevy, Roger T. Howe, and Tsu-Jae King Liu
2006 :
Chia-Pin Lin, National Chiao Tung University"Impact of Back Gate Bias on Hot-Carrier Effects of n-channel Tri-Gate FinFETs (TGFET)"
2005 :
Chung-Hsun Lin, University of California at Berkeley
"Compact Modeling of FinFETs Featuring Independent-Gate Operation Mode"