DAT Best Paper Award
Starting 2009, an Award Committee is formed for the selection of the Best Paper Award each year. The selection criteria of the award include the technical contents and writing quality of the paper as well as the quality of the presentation at the symposium. The award will be presented to the selected paper in the following year's symposium.
DAT Best Paper Award Committee
Led by the DAT Program Chairs, Dr. Shigeki Tomishima, Prof. Chih-Wei Liu and Prof. Ming-Der Shieh, the award committee members consist of subcommittee co-chairs. The Award Committee will select the 2023 DAT Best Paper Award based on the criteria including the technical contents and depth, quality of the paper as well as the quality of the presentation. The award will be announced after the conference and granted in the International VLSI Symposium on Technology, Systems and Applications opening ceremony in 2023. The winner will be rewarded by a certificate and US$500 . Besides, it will also offer the registration fee waived of 2023 International VLSI Symposium on Technology, Systems and Applications.
2022 DAT Best Paper Award Winners ~ Congratulations!
The 2022 DAT Best Paper Award will be granted in International VLSI Symposium on Technology, Systems and Applications opening ceremony in 2023 and the winner will be rewarded by a certificate and US$500. Besides, it will also offer the registration fee waived of 2023 International VLSI Symposium on Technology, Systems and Applications.
• A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement
Co-authors: Xingyu Wang, Ruilin Zhang, Yuxin Wang, Kunyang Liu, Xuanzhen Wang and Hirofumi Shinohara
Waseda University
• Distributed Sorting Architecture on Multiple FPGA
Co-authors: Yi-Da Hsin, Yen-Shi Kuo and Bo-Cheng Lai
National Yang Ming Chiao Tung University
2023 DAT Best Paper Award Candidates
• D1-1 A 7~10.5-Gb/s Reference-Less Linear Half-rate CDR Circuit Using Automatic Band Selector
Co-authors: Yi-En Hsu and Shen-Iuan Liu
National Taiwan University
• D1-2 A Sub-Sampling Phase-Locked Loop with a TDC-Based Frequency-Locked Loop
Co-authors: Yu-Meng Hong and Tsung-Hsien Lin
National Taiwan University
• D2-1 A 0.0072-mm2 10-bit 100-MS/s Calibration-free SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOS
Co-authors: Yao-Hung Tsai and Shen-Iuan Liu
National Taiwan University
• D4-1 A Novel Unified Modular Arithmetic Unit for Elliptic Curve Cryptography
Co-authors: Hsiang-Yu Chen, Kuan-Ying Peng and Kuen-Jong Lee
National Cheng Kung University
• D7-1 A Built-In Self-Calibration Scheme for Memristor-Based Spiking Neural Networks
Co-authors: Chi Tung, Kuan-Wei Hou and Cheng-Wen Wu
National Tsing Hua University
• D7-2 Machine Learning based Routing Guide Generation and its Application to Design Rule Violation Reduction
Co-authors: Chen-Han Lu1, Ting-Chi Wang1, Po-Yuan Chen2 and Chin-Fang Cindy Shen2
1 National Tsing Hua University
2 Synopsys Taiwan Co., Ltd.