Best Paper Award

   Starting 2009, an Award Committee is formed for the selection of the Best Paper Award each year. The selection criteria of the award include the technical contents and writing quality of the paper as well as the quality of the presentation at the symposium. The award will be presented to the selected paper in the following year's symposium. 

 

2018 VLSI-DAT Best Paper Award Committee 

    Led by the Technical Program Committee co-chairs, Prof. Hidetoshi Onodera and Prof. Ting-Chi Wang, the award committee members consist of subcommittee chairs and co-chairs. The Award Committee will select the 2018 Best Paper Award based on the criteria including the technical contents and depth, quality of the paper as well as the quality of the presentation. The award will be announced after the conference and granted in the VLSI-TSA & DAT Opening ceremony in 2019. The winner will be rewarded by a certificate and US$500 . Besides, it will also offer the registration fee waived of 2019 VLSI-DAT.


2017 Award Winners  ~ Congratulations !
 
The 2017 Best Paper Award will be granted in the VLSI-DAT Opening ceremony in 2018 and the winner will be rewarded by a certificate and US$500 . Besides, it will also offer the registration fee waived of 2018 VLSI-DAT.
 
• Low-Latency Voltage-Racing Winner-Take-All (VR-WTA) Circuit for Acceleration of Learning Engine
  Co-authors: Chai-Heng Wu, Ting-Sheng Chen, Ding-Yuan Lee, Tsung-Te Liu, and An-Yeu (Andy) Wu
                    National Taiwan University, Taiwan  
 
• 

Robust Test Pattern Generation for Hold-time Faults in Nanometer Technologies

   Co-authors: Yu-Hao Ho, Yo-Wei Chen, Chih-Ming Chang, Kai-Chieh Yang, and Chien-Mo Li
                       National Taiwan University, Taiwan
 
2018 Candidates of Best Paper Award
 
• D6-1 TSV-Aware 3D Test Wrapper Chain Optimization
   Co-authors: Yu-Yi Wu and Shih-Hsu Huang
                     Chung Yuan Christian University
 
• D7-1 A 1.86mJ/Gb/Query Bit-Plane Payload Machine Learning Processor in 90nm CMOS
   Co-authors: Fang-Ju Ku, Tung-Yu Wu, Yen-Chin Liao, Hsie-Chia Chang, Wing Hung Wong and Chen-Yi Lee
                     National Chiao Tung University
 
• D11-1 Using Range-equivalent Circuits for Facilitating Bounded Sequential Equivalence Checking
   Co-authors: Yung-Chih Chen, Wei-An Ji, Chih-Chung Wang,Ching-Yi Huang, Chia-Cheng Wu, Chia-Chun Lin
                     and Chun-Yao Wang 
                     National Tsing Hua University
 
D14-1 A High Learning Capability Probabilistic Spiking Neural Network Chip
  Co-authors:Hung-Yi Hsieh, Pin-Yi Li, Cheng-Han Yang and Kea-Tiong Tang
                   National Tsing Hua University  
 
 
> History of the VLSI-DAT Best Paper Award
 
> History of the VLSI-DAT Other Awards