J2 Design and Technology Co-optimization

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    J2 Analysis of Thermal Effects in Integrated Radio Transmitters
    Christian Fager
    Chalmers University of Technology, Sweden 
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    J2 Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic pathfinding DTCO of advanced transistors
    Stanley Seungchul Song
    Qualcomm, USA
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    J2 Systematic Co-Optimization From Chip Design, Process Technology To Systems For GPU AI Chip And Autonomous Driving SOC
    John Hu
    NVIDIA, USA

J5 Technology and Design Challenges for Next Generation Communication

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    J5 Emerging Technologies and Concepts for 5G Applications
    Wolfgang Bösch
    Graz University of Technology, Austria 
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    J5 GaN-based digital transmitter architectures for 5G
    Florian Hühn
    FBH-Berlin, Germany
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    J5 Antenna-in-Package Design and Module Integration for Millimeter-Wave Communication and 5G
    Xiaoxiong Gu
    IBM, USA 

T2 Application of FET/Integration Technologies to Bio-sensing

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    T2-1 High-Mobility Polymer Field-Effect Transistor Based-Sensor Array for Selective Discrimination between Multiple Isomers
    Hossam Haick
    Technion – Israel Institute of Technology, Israel
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    T2-2 Integrated Molecule Recognition Sensor Electronics using Nanostrcured Metal Oxide on Silicon
    Takeshi Yanagida
    Kyushu University, Japan
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    T2-3 Nanomechanical Sensors with AI towards Standard Olfactory IoT Sensing System
    Genki Yoshikawa
    NIMS, Japan
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    T2-4 On the Detection, Characterization, and Identification of Single Molecule with Nanopores
    John J. Kasianowicz
    NIST, USA 

T5 Ferroelectrics on Si Technology

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    T5-1 Hafnium oxide based ferroelectric devices for memories and beyond
    Thomas Mikolajick
    NaMLab gGmbH and TU Dresden, Germany 
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    T5-2 Negative Capacitance Transistors
    Sayeef Salahuddin
    University of California, Berkeley, USA 
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    T5-3 Device physics, design and challenge of Negative Capacitance FET
    Gengchiau Liang
    National University of Singapore, Singapore

T8 Future Patterning Solutions

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    T8-1 Stochastic Limitations to EUV Lithography
    Chris A. Mack
    Fractilia, LLC, USA 
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    T8-2 Novel Patterning schemes and technologies for the sub 5nm era
    Angélique Raley
    Tokyo Electron Ltd., USA 
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    T8-3 Approaches and opportunities for area-selective atomic layer deposition
    Adrie Mackus
    Eindhoven University of Technology,  USA
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    T8-4 Highly CMOS-compatible & Cost-efficient Patterning with Tilted-ion Implantation
    Sangwan Kim
    Ajou University, Korea 

T9 Magnetic Materials & Memory

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    T9-1 STT-MRAM for embedded memory applications from eNVM to Last Level Cache
    Po-Kang Wang
    Headway Technologies, USA 
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    T9-2 Novel nanopatterning approach and improvements in STT-MRAM stacks for high density memory operation
    Bernard Dieny
    SPINTEC and CEA/Grenoble, France
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    T9-3 Voltage-Control Spintronics Memory Having Potentials for High-Density and High-Speed Applications
    Hiroaki Yoda
    Toshiba Corporation, Japan 
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    T9-4 Antiferromagnetic Magneto-electric Memory and Logic
    Peter Dowben
    University of Nebraska, USA 

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