D1 Clocking Techniques

  • D1-1 A 25-Gb/s 13 mW Clock and Data Recovery Using C2MOS D-Flip-Flop in 65-nm CMOS
    Ryosuke Noguchi, Kosuke Furuichi, Hiromu Uemura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Hiroaki Katsurai, Shinsuke Nakano and Hideyuki Nosaka, University of Shiga Prefecture
  • D1-2 Design of Divider Circuit for Electrochemical Impedance Spectroscopy Measurement System
    Siang-Wei Wang, Tse-An Chen, Kuan-Hung Chen and Chia-Ling Wei, National Cheng Kung University
  • D1-3 A ∆Σ DPLL with 1b TDC, 4b DTC and 8-Tap FIR Filter for Low-Voltage Clock Generation/Modulation Systems
    Xiaohua Huang, Han Liu, Woogeun Rhee and Zhihua Wang, Tsinghua University
    Sheng–Lyang Jang, Ke Jen Lin, Wen Cheng Lai and Miin-Horng Juang, National Taiwan University of Science and Technology

D2 Analog Interface Circuits

  • D2-1 A 473μW Wireless 16-Channel Neural Recording SoC with RF Energy Harvester
    Kun-Ying Yeh, Yu-Jie Huang, Tung-Chien Chen, Liang-Gee Chen and  Shey-Shi Lu, National Taiwan University
  • D2-2 A Cuffless Wearable System for Real-time Cutaneous Pressure Monitoring with Cloud Computing Assistance
    Kun-Ying Yeh, Ting-Hao Lin, Yi-Yen Hsieh, Chia-Ming Chang, Yao-Joe Yang and Shey-Shi Lu, National Taiwan University
  • D2-3 A 12-bit 1-MS/s SAR ADC with a Hybrid DAC in 180 nm CMOS
    Yung-Hui Chung, Chia-Hui Tien and Che-Wei Chang, National Taiwan University of Science and Technology
  • D2-4 A 11-Bit 35-MS/s Wide Input Range SAR ADC in 180-nm CMOS Process
    Wen-Chia Luo, Soon-Jyh Chang, Chun-Po Huang and Hao-Sheng Wu, National Cheng Kung University

D3 Circuits and Systems for Networking and Security

  • D3-1 High-Throughput Von Neumann Post-Processing for Random Number Generator
    Ruilin Zhang, Sijia Chen, Chao Wan and Shinohara Hirofumi, Waseda University
  • D3-2 High-Performance NTT Architecture for Large Integer Multiplication
    Jheng-Hao Ye and Ming-Der Shieh, National Cheng Kung University
  • D3-3 28nm Near/Sub-Threshold Dual-Port FIFO Memory for Shared Queues in Multi-Sensor Applications
    Yi-Chun Wu, Po-Tsang Huang, Shun-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang and Ching-Te Chuang, National Chiao Tung University

D5 Power Management Techniques

  • D5-1 A High-Performance Current-Mode DC-DC Buck Converter with Adaptive Clock Control Technique
    You-Te Chiu, Yu-Hsuan Liu, and Chung-Chih Hung, National Chiao Tung University
  • D5-2 A Digital Peak Current Delay Compensation for Primary-Side Regulation Flyback Adapter
    Chun-Ping Niou, Ta-Jin Chen and Chien-Hung Tsai, National Cheng Kung University
  • D5-3 A 6.78MHz Active Voltage Doubler with Near-Optimal On/Off Delay Compensation for Wireless Power Transfer Systems
    Fangyu Mao, Yan Lu, Seng-Pan U and Rui P., Martins University of Macau

D6 Testing

  • D6-1 TSV-Aware 3D Test Wrapper Chain Optimization
    Yu-Yi Wu and  Shih-Hsu Huang, Chung Yuan Christian University
  • D6-2 Hold Violation Analysis for Functional Test of Ultra-Low Temperature Circuits at Room Temperature
    Takahiro Nakayama and  Masanori Hashimoto, Osaka University
  • D6-3 Parallel Order ATPG for Test Compaction
    Yu-Wei Chen, Yu-Hao Ho, Chih-Ming Chang, Kai-Chieh Yang, Ming-Ting Li and James Chien-Mo Lee, National Taiwan University

D7 Novel digital systems and emerging technology

  • D7-1 A 1.86mJ/Gb/Query Bit-Plane Payload Machine Learning Processor in 90nm CMOS
    Fang-Ju Ku, Tung-Yu Wu, Yen-Chin Liao, Hsie-Chia Chang, Wing Hung Wong and Chen-Yi Lee, National Chiao Tung University
  • D7-2 Hardware Design of Disparity Computation for Stereo Vision Using Guided Image Filtering
    Shen-Fu Hsiao and Chih-Hsuan Chang, National Sun Yat-Sen University
  • D7-3 Using Approximate Circuits to Counter Process Imperfections in CNFET based Circuits
    Kaship Sheikh and Lan Wei, University of Waterloo
  • D7-4 The Application of Non-volatile Look-up-table Operations based on Multilevel-cell of Resistance Switching Random Access Memory
    Lan Dai, Dongyu Fan, Feng Zhang, Chengying Chen, Qipeng Lin and Haihua Shen, North China University of Technology

D9 Advances in Physical Design and Verification

  • D9-1 A Learning-Based Methodology for Routability Prediction in Placement
    Li-Chin Chen, Chien-Chia Huang, Yao-Ling Chang and Hung-Ming Chen, National Chiao Tung University 
  • D9-2 Triple Patterning Lithography-aware Detailed Routing Ensuring Via Layer Decomposability
    Hua-Yi Wu and Shao-Yun Fang, National Taiwan University of Science and Technology
  • D9-3 Diagnosis and Repair of Cells (DRC) Responsible for Power-Supply-Noise Violations
    Yu-Ching Li, Shih-Yao Lin, Heng-Yi Lin, and James Chien-Mo Li, LaDS
  • D9-4 MapReduce-Based Pattern Classification for Design Space Analysis
    Yan-Shiun Wu, Hong-Yan Su, Yi-Hsiang Chang, Rasit Onur Topaloglu and Yih-Lang Li, National Chiao Tung University

D11 Emerging Techniques in EDA

  • D11-1 Using Range-equivalent Circuits for Facilitating Bounded Sequential Equivalence Checking
    Yung-Chih Chen, Wei-An Ji, Chih-Chung Wang, Ching-Yi Huang, Chia-Cheng Wu, Chia-Chun Lin and Chun-Yao Wang, National Tsing Hua University
  • D11-2 Optimization of Threshold Logic Networks with ODC-based Node Merging
    Fu-Lian Wong, Li-Cheng Zheng and Yung-Chih Chen, Yuan Ze University
  • D11-3 An Ising Model Mapping to Solve Rectangle Packing Problem
    Kotaro Terada, Daisuke Oku, Sho Kanamaru, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa and Nozomu Togawa, Waseda University
  • D11-4 SOLAR: Simultaneous Optimization of Control-Layer Pins Placement and Channel Routing in Flow-Based Microfluidic Biochips
    Jia-Lin Wu, Katherine Shu-Min Li, Jain-De Li, Sying-Jyan Wang  and Tsung-Yi Ho, National Chung Hsing University

D14 Energy Efficient Systems for Emerging Applications

  • D14-1 A High Learninig Capability Probabilistic Spiking Neural Network Chip
    Hung-Yi Hsieh, Pin-Yi Li, Cheng-Han Yang and Kea-Tiong Tang, National Tsing Hua University
  • D14-2 DrowsyNet: Convolutional Neural Networks with Runtime Power-Accuracy Tunability Using Inference-Stage Dropout
    Ren-Shuo Liu, Yun-Chen Lo, Yuan-Chun Lo, Chih-Yu Shen and  Cheng-Ju Lee, National Tsing Hua University
  • D14-3 MORAS: An Energy-Scalable System using Adaptive Voltage Scaling
    Kuo-Chiang Chang, Shien-Chun Luo, Ching-Ji Huang, Jia-Hung Peng, and Yuan-Hua Chu, Industrial Technology Research Institute

D16 Architecture and Applications of Embedded Systems

  • D16-1 Double Asymmetric-latency Storage Class Memories (SCMs) for Fast-Write SCM, Fast-Read SCM & NAND Flash Hybrid SSDs
    Yutaka Adachi, Chihiro Matsui and Ken Takeuchi, Chuo University
    Kun-Chih Chen and Po-Cheng Chien, National Sun Yat-Sen University
  • D16-3 Accurate and Fast Obstacle Detection Method for Automotive Applications Based on Stereo Vision
    Yi-Chin Tsai, Jih-Hsiang Cheng, Yun Chen and Kuan-Hung Chen, FengChia University