Best Paper Award

   Starting 2009, an Award Committee is formed for the selection of the Best Paper Award each year. The selection criteria of the award include the technical contents and writing quality of the paper as well as the quality of the presentation at the symposium. The award will be presented to the selected paper in the following year's symposium. 

 

2017 VLSI-DAT Best Paper Award Committee 

    Led by the Technical Program Committee co-chairs, Dr. Wu-Tung Cheng and Prof. Lih-Yih Chiou, the award committee members consist of subcommittee chairs and co-chairs. The Award Committee will select the 2017 Best Paper Award based on the criteria including the technical contents and depth, quality of the paper as well as the quality of the presentation. The award will be announced after the conference and granted in the VLSI-TSA & DAT Opening ceremony in 2018. The winner will be rewarded by a certificate and US$500 . Besides, it will also offer the registration fee waived of 2018 VLSI-DAT.


2016 Award Winners  ~ Congratulations !
 
The 2016 Best Paper Award will be granted in the VLSI-DAT Opening ceremony in 2017 and the winner will be rewarded by a certificate and US$500 . Besides, it will also offer the registration fee waived of 2017 VLSI-DAT.
 
• A 7 GB/S Half-Rate Clock and Data Recovery Circuit with Compact Control Loop
  Co-authors: Yu-Po Cheng, Yen-Long Lee, Ming-Hung Chien, and Soon-Jyh Chang
                   National Cheng Kung University, Taiwan  
 
• 

Overlay-aware Layout Legalization for Self-Aligned Double Patterning Lithography

   Co-authors: Chong-Meng Huang and Shao-Yun Fang
                         National Taiwan University of Science and Technology, Taiwan
 
2017 Candidates of Best Paper Award 
 
• D1-1 Low-Latency Voltage-Racing Winner-Take-All (VR-WTA) Circuit for Acceleration of Learning Engine
          Co-authors: Chai-Heng Wu, Ting-Sheng Chen, Ding-Yuan Lee, Tsung-Te Liu, and An-Yeu (Andy) Wu
          National Taiwan University, Taiwan
 
• D2-3 

A 45 μW, 9.5 MHz Current-Reused RC Oscillator Using a Swing-Boosting Technique

          Co-authors: Shao-Yung Lu and Yu-Te Liao
          National Chiao Tung University, Taiwan
 
• D5-1 

Design Space Exploration with a Cycle-accurate SystemC/TLM DRAM Controller Model

           Co-authors: Ting-Shuo Hsu, Chao-Chih Wu, Che-Wei Hsu, Chih-Tsun Huang, Jing-Jia Liou,
           Yao-Hua Chen, and Juin-Ming Lu
           National Tsing Hua University, Taiwan
 
• D7-1

A Four-band TD-LTE Transmitter with Wide Dynamic Range and LPF Bandwidth Calibration

          Co-authors: Zhen Liang, Bin Li, Mo Huang, Hui Ye, Ken Xu, Yutao Liu, and Yan Lu
          South China University of Technology, China
 
• D9-1

A 6.4G LLR/s 8x8 64-QAM Soft-Output MIMO Detector with Lattice Reduction Preprocessing

           Co-authors: Jing-You Lin, Jung-Chun Chi, Chun-Fu Liao, and Yuan-Hao Huang
           National Tsing Hua University, Taiwan
 
• D11-1

Robust Test Pattern Generation for Hold-time Faults in Nanometer Technologies

            Co-authors: Yu-Hao Ho, Yo-Wei Chen, Chih-Ming Chang, Kai-Chieh Yang, and Chien-Mo Li
            National Taiwan University, Taiwan
 
• D14-1

Detailed Routing Violation Prediction During Placement Using Machine Learning

            Co-authors: Aysa Fakheri Tabrizi, Nima Karimpour Darav, Logan Rakai, Andrew Kennings,
            and Laleh Behjat
            University of Calgary, Canada
 
 
> History of the VLSI-DAT Best Paper Award
 
> History of the VLSI-DAT Other Awards