D1 Sub-Systems for Medical Applications

1:30 PM~2:50 PM,Monday , April 25 Ballroom D ( 11F )
  • D1-1 A 13.56-MHz Passive NFC Tag IC in 0.18-μm CMOS Process for Biomedical Applications
    1:30 PM~1:50 PM,Monday , April 25
    Chi-Huan Lu,Ji-An Li, and Tsung-Hsien Lin
    National Taiwan University, Taiwan 
  • D1-2 Multiple Output Switched Capacitor DC-DC Converter with Capacitor Sharing for Sensor-Fusion Platforms
    1:50 PM~2:10 PM,Monday , April 25
    Yu-Jie Liang, Po-Hung Chen, Yuan-Hua Chu, and Wei Hwang
    National Chiao Tung University, Taiwan
  • D1-3 A Low-Power Oscillator-Based Readout Interface for Medical Ultrasonic Sensors
    2:10 PM~2:30 PM,Monday , April 25
    Teng-Chuan Cheng, Chih-Wei Chen Hsu, Hui-Chun Wang, and Tsung-Heng Tsai
    National Chung Cheng University, Taiwan 

D2 Design and Implementation for Many-Core Systems

3:10 PM~4:30 PM,Monday , April 25 Ballroom D ( 11F )
  • D2-1 Architecture Agnostic Energy Model for GPU-based Design
    3:10 PM~3:30 PM,Monday , April 25
    Arthur Marmin, Chun-Hung Lai, Haruyuki Tago, Hsun-Lun Huang, and Juin-Ming Lu
    Industrial Technology Research Institute, Taiwan 
  • D2-2 Sniper-TEVR: Core-Variation Simulation Platform with Register-Level Fault Injection for Robust Computing in CMP System
    3:30 PM~3:50 PM,Monday , April 25
    Ching-Yao Chou, Yi-Chieh Ho, Huai-Ting Li, and An-Yeu (Andy) Wu
    National Taiwan University, Taiwan 
  • D2-3 Interference-Aware Batch Memory Scheduling in Heterogeneous Multicore Architecture
    3:50 PM~4:10 PM,Monday , April 25
    Chun-Hsien Lu, Hung-Lin Chao, Yi-Chien Song, and Pao-Ann Hsiung
    National Chung Cheng University, Taiwan 
  • D2-4 Scalable Mutli-Layer Barrier Synchronization on NoC
    4:10 PM~4:30 PM,Monday , April 25
    Yu-Lun Tzeng, Kun-Hua Huang, and Bo-Cheng Charles Lai
    National Chiao Tung University, Taiwan 

D5 Intelligent and Efficient System Design

4:50 PM~6:10 PM,Monday , April 25 Ballroom D ( 11F )
  • D5-1 Microcontroller Implementation of Low-Power Compression for Wearable Biosignal Transmitter
    4:50 PM~5:10 PM,Monday , April 25
    Yu-Chia Yu, Chen-Ming Nien, and Robert Rieger
    National Sun Yat-Sen University, Taiwan
  • D5-2 An Efficient and Effective Performance Estimation Method for DSE
    5:10 PM~5:30 PM,Monday , April 25
    Chen Lin, Xueliang Du, Xinwei Jiang, and Donglin Wang
    The Institute of Automation,Chinese Academy of Sciences (CASIA), China 
  • D5-3 A Smart Surveillance System with Multiple People Detection, Tracking, and Behavior Analysis
    5:30 PM~5:50 PM,Monday , April 25
    Chia-Jui Yang, Ting Chou, Fong-An Chang, and Jiun-In Guo

    National Chiao Tung University, Taiwan
  • D5-4 Design and Implementation of a Dangerous Driving Behavior Analysis System
    5:50 PM~6:10 PM,Monday , April 25
    Chun-Yu Chung, Yi-Ting Lai, and Jiun-In Guo
    National Chiao Tung University, Taiwan 

D6 Low-Power Low-Voltage Analog Circuit Designs

10:20 AM~11:20 AM,Tuesday , April 26 Ballroom D ( 11F )
  • D6-1 A 70nW, 0.3V Temperature Compensation Voltage Reference Consisting of Subthreshold MOSFETs in 65nm CMOS Technology
    10:20 AM~10:40 AM,Tuesday , April 26

    Ting-Chou Lu1, 2, Ming-Dou Ker2, and Hsiao-Wen Zan2
    1Industrial Technology Research Institute, Taiwan.
    2National Chiao Tung University, Taiwan.
  • D6-2 A Precise Decibel-Linear Programmable-Gain Amplifier for Ultrasound Imaging Receivers
    10:40 AM~11:00 AM,Tuesday , April 26
    Pei-Keng Tsai, Po-Chih Ku, Chih-Cheng Lu, Chih-Cheng Lu, and Liang-Hung Lu
    National Taiwan University, Taiwan 
  • D6-3 An Analog Front-End with Fast Motion Artifact Recovery for Bio-Signal Recording
    11:00 AM~11:20 AM,Tuesday , April 26
    Yu-Ting Jhong and Po-Chiun Huang
    National Tsing Hua University, Taiwan 

D7 Advances in Lithography

10:20 AM~11:20 AM,Tuesday , April 26 Mezzanine A+B ( 13F )
  • D7-1 Overlay-aware Layout Legalization for Self-Aligned Double Patterning Lithography
    10:20 AM~10:40 AM,Tuesday , April 26
    Chong-Meng Huang and Shao-Yun Fang
    National Taiwan University of Science and Technology, Taiwan
  • D7-2 Trim Mask Optimization for Hybrid Multiple Pattering Lithography
    10:40 AM~11:00 AM,Tuesday , April 26
    Yin-Lu Chang and Shao-Yun Fang
    National Taiwan University of Science and Technology, Taiwan 
  • D7-3 A Lithographic Mask Manufacturability and Pattern Fidelity Aware OPC Algorithm
    11:00 AM~11:20 AM,Tuesday , April 26
    Ahmed Awad and Atsushi Takahashi
    Tokyo Institute of Technology, Japan 

D8 Low-Power / High-Performance VLSI Architecture

11:30 AM~12:30 PM,Tuesday , April 26 Ballroom D ( 11F )
  • D8-1 An Energy-Efficient Nonvolatile Microprocessor Considering Software-Hardware Interaction for Energy Harvesting Applications
    11:30 AM~11:50 AM,Tuesday , April 26
    Tsai-Kan Chien1,2, Lih-Yih Chiou1 , Chang-Chia Lee1 , Yao-Chun Chuang1 , Shien-Han Ke 1, Shyh-Shyuan Sheu2 , Heng-Yuan Li2 , Pei-Hua Wang2 , Tzu-Kun Ku2 , Ming-Jinn Tsai2 , and Chih-I Wu2 
    1 National Cheng Kung University, Taiwan
    2 Industrial Technology Research Institute, Taiwan
     
  • D8-2 High Performance VLSI Architecture for 3-D Discrete Wavelet Transform
    11:50 AM~12:10 PM,Tuesday , April 26
    B.K.N.Srinivasarao, and Indrajit Chakrabarti
    Indian Institute of Technology Kaharagpur, India
     
  • D8-3 A Variable-Latency, Ultra-Low-Voltage RISC Processor with a New In-Situ Error Detection and Correction Techniques
    12:10 PM~12:30 PM,Tuesday , April 26
    Chi-Chun Lin, Kuo-Chiang Chang, and Chih-Wei Liu
    National Chiao Tung University, Taiwan 

D9 Advanced TPG Technologies

11:30 AM~12:30 PM,Tuesday , April 26 Mezzanine A+B ( 13F )
  • D9-1 Test Coverage Debugging for Designs with Timing Exception Paths
    11:30 AM~11:50 AM,Tuesday , April 26
    Kun-Han Tsai
    Mentor Graphics, USA  
  • D9-2 An IR-Drop Guided Test Pattern Generation Technique
    11:50 AM~12:10 PM,Tuesday , April 26
    Li-Chen Tsai, Jiun-Zong Li, Yi-Tsung Lin, Jiun-Lang Huang, Ann Shih, and Zoe F. Conroy
    National Taiwan University, Taiwan 
  • D9-3 On Gate Function Based Tests for Scan Designs
    12:10 PM~12:30 PM,Tuesday , April 26
    Xijiang Lin1 and Sudhakar M. Reddy2
    1 Mentor Graphics, USA
    2 University of Iowa, USA

D10 Data Converters and Circuit Techniques

1:30 PM~2:50 PM,Tuesday , April 26 Ballroom D ( 11F )
  • D10-1 A 12b 10MS/s 18.9fJ/Conversion-Step Sub-Radix-2 SAR ADC
    1:30 PM~1:50 PM,Tuesday , April 26
    Kwuang-Han Chang, and Chih-Cheng Hsieh
    National Tsing-Hua University, Taiwan
  • D10-2 A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS Process
    1:50 PM~2:10 PM,Tuesday , April 26
    Chia-Hsin Lee1,2, Chih-Huei Hou1, Chun-Po Huang1, Soon-Jyh Chang1 ,Yuan-Ta Hsiehand Ying-Zong Juang2
    1 National Cheng Kung University, Taiwan
    2 National Chip Implementation Center, Taiwan
  • D10-3 DAC Linearity Improvement Algorithm With Unit Cell Sorting Based on Magic Square
    2:10 PM~2:30 PM,Tuesday , April 26
    Masashi Higashino1, Shaiful Nizam Mohyar2, and Haruo Kobasashi1
    1 Gunma University, Japan
    2 Universiti Malaysia Perlis, Malaysia
  • D10-4 Fundamental Design Consideration of Sampling Circuit
    2:30 PM~2:50 PM,Tuesday , April 26
    Keita Kurihara1, Kensuke Kobayashi2, Masafumi Uemori1, Miho Arai1, and Haruo Kobayashi1
    1 Gunma University, Japan
    2 Technical Consultant, Penang, Malaysia



D11 Digital Communication Systems

1:30 PM~2:50 PM,Tuesday , April 26 Mezzanine A+B ( 13F )
  • D11-1 Linear Precoding and Adaptive Multi-Taper Spectrum Detector for Cognitive Radios
    1:30 PM~1:50 PM,Tuesday , April 26
    Yi-Han Tseng, Terng-Hsing Chiu, Jung-Mao Lin, and Hsi-Pin Ma
    National Tsing Hua University, Taiwan
  • D11-2 Temperature Tracking Scheme for Programmable Phase-Shifter in Pulsed Radar SoC
    1:50 PM~2:10 PM,Tuesday , April 26
    Yun-Jia Liao and Shi-Yu Huang
    National Tsing Hua University, Taiwan 
  • D11-3 Time-Domain Characteristics of Body Channel Communication (BCC) and BCC Transceiver Design
    2:10 PM~2:30 PM,Tuesday , April 26
    Ching-Che Chung, Chih-Yu Lin, and Jia-Zong Yang
    National Chung Cheng University, Taiwan 

D12 Fast Transceiver Circuit Techniques

3:10 PM~4:30 PM,Tuesday , April 26 Ballroom D ( 11F )
  • D12-1 A 7 GB/S Half-Rate Clock and Data Recovery Circuit with Compact Control Loop
    3:10 PM~3:30 PM,Tuesday , April 26
    Yu-Po Cheng, Yen-Long Lee, Soon-Jyh Chang, and Ming-Hung Chien
    National Cheng Kung University, Taiwan
  • D12-2 A 2x25Gb/s 20mW Serializing Transmitter with 2.5:1 Multiplexers in 40nm Technology
    3:30 PM~3:50 PM,Tuesday , April 26
    Bo-Jing Lin and Tai-Cheng Lee
    National Taiwan University, Taiwan
  • D12-3 A Hybrid Frequency/Phase-Locked Loop for Versatile Clock Generation with Wide Reference Frequency Range
    3:50 PM~4:10 PM,Tuesday , April 26
    Sitao Lv, Ni Xu, Woogeun Rhee, and Zhihua Wang
    Tsinghua University, China
  • D12-4 The LED Driver IC of Visible Light Communication with High Data Rate and High Efficiency
    4:10 PM~4:30 PM,Tuesday , April 26

    Yu-Chen Lee, Jyun-Liang Lai, and Chueh-Hao Yu

    Industrial Technology Research Institute, Taiwan

D13 Advances in Layout Synthesis

3:10 PM~4:30 PM,Tuesday , April 26 Mezzanine A+B ( 13F )
  • D13-1 An Integrated Placement and Routing for Ratioed Capacitor Array based on ILP Formulation
    3:10 PM~3:30 PM,Tuesday , April 26
    Pang-Yen Chou, Mark Po-Hung Lin, and Helmut Graeb
    Technical University of Munich, Germany
  • D13-2 Automatic Synthesis Flow for Voltage Rectifiers with Impedance Consideration
    3:30 PM~3:50 PM,Tuesday , April 26
    Fang-Yu Jhou, Chang-Han Wang, Tsung-Yueh Wu, Yu-Kang Lou, and Chien-Nan Jimmy Liu
    National Central University, Taiwan
  • D13-3 Area Minimization Method for CMOS Circuits Using Constraint Programming in 1D-Layout Style
    3:50 PM~4:10 PM,Tuesday , April 26
    Hayato Mashiko and Yukihide Kohira
    The University of Aizu, Japan
  • D13-4 ThermPL: Thermal-Aware Placement Based on Thermal Contribution and Locality
    4:10 PM~4:30 PM,Tuesday , April 26
    Jiaxing Song, Yu-Min Lee, and Chia-Tung Ho
    National Chiao Tung University, Taiwan

D15 Biomedical Circuits and Systems

10:20 AM~11:20 AM,Wednesday , April 27 Ballroom D ( 11F )
  • D15-1 A 98.6uW Acoustic Signal Processor for Fully-Implantable Cochlear Implants
    10:20 AM~10:40 AM,Wednesday , April 27
    Hao-Min Liu1, Yung-Jen Lin1, Yu-Chi Lee1, Cheng-Yen Lee1, and Chia-Hsiang Yang2
    1 National Chiao Tung University, Taiwan
    2 National Taiwan University, Taiwan
  • D15-2 A 1.4 mW Low-Power Feed-Back FxLMS ANC VLSI Design for In-Ear Headphones
    10:40 AM~11:00 AM,Wednesday , April 27
    Hong-Son Vu and Kuan-Hung Chen
    Feng Chia University, Taiwan
  • D15-3 A Multi-Axis Readout Circuit Using in Female Ovulation Monitoring Platform
    11:00 AM~11:20 AM,Wednesday , April 27
    Hsin-Yi Yu, Kelvin Yi-Tse Lai, Hsie-Chia Chang, and Chen-Yi Lee
    National Chiao Tung University, Taiwan

D16 System-Level Synthesis and Design

10:20 AM~11:20 AM,Wednesday , April 27 Mezzanine A+B ( 13F )
  • D16-1 2.5D System Synthesis Methodology under Performance, Power and Thermal Constraints
    10:20 AM~10:40 AM,Wednesday , April 27
    Chung-Han Chou, Zhi-Yang Wang, Tsui-Yun Chang, Shih-Hsu Huang, and Shih-Chieh Chang
    National Tsing Hua University, Taiwan
  • D16-2 Guidelines for Effective and Simplified Dynamic Supply and Threshold Voltage Scaling
    10:40 AM~11:00 AM,Wednesday , April 27
    Toshinori Takeshita, Tohru Ishihara, and Hidetoshi Onodera
    Kyoto University, Japan
  • D16-3 A High-Level Synthesis Algorithm for FPGA Designs Optimizing Critical Path with Interconnection-Delay and Clock-Skew Consideration
    11:00 AM~11:20 AM,Wednesday , April 27
    Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, and Nozomu Togawa
    Waseda University, Japan

D18 Nanometer Memory Designs

11:30 AM~12:30 PM,Wednesday , April 27 Ballroom D ( 11F )
  • D18-1 28nm Ultra-Low Power Near-/Sub-threshold First-In-First-Out (FIFO) Memory for Multi-Bio-Signal Sensing Platforms
    11:30 AM~11:50 AM,Wednesday , April 27
    Wei-Shen Hsu, Po-Tsang Huang, Shun-Lin Wu, Ching-Te Chuang, Wei Hwang, Ming-Hsien Tu,
    and Ming-Yu Yin
    National Chiao Tung University, Taiwan
  • D18-2 A 128-kb 25% Power Reduced 1T High Density ROM with 0.55 ns Access Time using Low Swing Bitline Edge Sensing in 16nm FinFET Technology
    11:50 AM~12:10 PM,Wednesday , April 27
    Sachin Taneja, Vaibhav Verma, and Prashant Dubey
    synopsys india private limited, India
  • D18-3 A 1V 800MHz 140Kb Register File Compiler using Variation Aware Self-Timing in 40nm Bulk CMOS
    12:10 PM~12:30 PM,Wednesday , April 27
    Vivek Kumar Dikshit, Prashant Dubey, and Rachit Dave
    synopsys india private limited, India

D19 Emerging Technologies for Highly Reliable System

11:30 AM~12:30 PM,Wednesday , April 27 Mezzanine A+B ( 13F )
  • D19-1 3D-IC Test Architecture for TSVs with Different Impact Ranges of Crosstalk Faults
    11:30 AM~11:50 AM,Wednesday , April 27
    Wen Hsuan Hsu, Michael Kochte, and Kuen Jong Lee
    National Cheng Kung University, Taiwan
  • D19-2 SERL: Soft Error Resilient Latch Design
    11:50 AM~12:10 PM,Wednesday , April 27
    Chun-Wei (Jacky) Chang, Hsuan-Ming (Ryan) Huang, Yuwen Lin, and Charles H.-P. Wen
    National Chiao Tung University, Taiwan
  • D19-3 A Test-per-Cycle BIST Architecture with Low Area Overhead and No Storage Requirement
    12:10 PM~12:30 PM,Wednesday , April 27
    Chung-Min Shiao, Wei-Cheng Lien, and Kuen-Jong Lee
    National Cheng Kung University, Taiwan

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